1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*af930827SMasahiro Yamada */ 6*af930827SMasahiro Yamada 7*af930827SMasahiro Yamada #ifndef AT91_TC_H 8*af930827SMasahiro Yamada #define AT91_TC_H 9*af930827SMasahiro Yamada 10*af930827SMasahiro Yamada typedef struct at91_tcc { 11*af930827SMasahiro Yamada u32 ccr; /* 0x00 Channel Control Register */ 12*af930827SMasahiro Yamada u32 cmr; /* 0x04 Channel Mode Register */ 13*af930827SMasahiro Yamada u32 reserved1[2]; 14*af930827SMasahiro Yamada u32 cv; /* 0x10 Counter Value */ 15*af930827SMasahiro Yamada u32 ra; /* 0x14 Register A */ 16*af930827SMasahiro Yamada u32 rb; /* 0x18 Register B */ 17*af930827SMasahiro Yamada u32 rc; /* 0x1C Register C */ 18*af930827SMasahiro Yamada u32 sr; /* 0x20 Status Register */ 19*af930827SMasahiro Yamada u32 ier; /* 0x24 Interrupt Enable Register */ 20*af930827SMasahiro Yamada u32 idr; /* 0x28 Interrupt Disable Register */ 21*af930827SMasahiro Yamada u32 imr; /* 0x2C Interrupt Mask Register */ 22*af930827SMasahiro Yamada u32 reserved3[4]; 23*af930827SMasahiro Yamada } at91_tcc_t; 24*af930827SMasahiro Yamada 25*af930827SMasahiro Yamada #define AT91_TC_CCR_CLKEN 0x00000001 26*af930827SMasahiro Yamada #define AT91_TC_CCR_CLKDIS 0x00000002 27*af930827SMasahiro Yamada #define AT91_TC_CCR_SWTRG 0x00000004 28*af930827SMasahiro Yamada 29*af930827SMasahiro Yamada #define AT91_TC_CMR_CPCTRG 0x00004000 30*af930827SMasahiro Yamada 31*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 32*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 33*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 34*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 35*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 36*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_XC0 0x00000005 37*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_XC1 0x00000006 38*af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_XC2 0x00000007 39*af930827SMasahiro Yamada 40*af930827SMasahiro Yamada typedef struct at91_tc { 41*af930827SMasahiro Yamada at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ 42*af930827SMasahiro Yamada u32 bcr; /* 0xC0 TC Block Control Register */ 43*af930827SMasahiro Yamada u32 bmr; /* 0xC4 TC Block Mode Register */ 44*af930827SMasahiro Yamada } at91_tc_t; 45*af930827SMasahiro Yamada 46*af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 47*af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 48*af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 49*af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 50*af930827SMasahiro Yamada 51*af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 52*af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 53*af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 54*af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C 55*af930827SMasahiro Yamada 56*af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 57*af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 58*af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 59*af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 60*af930827SMasahiro Yamada 61*af930827SMasahiro Yamada #endif 62