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/rk3399_ARM-atf/fdts/
H A Dstm32mp151.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
22 nvmem-cells = <&part_number_otp>;
34 #interrupt-cells = <3>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
[all …]
H A Dstm32mp251.dtsi12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
29 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
61 #interrupt-cells = <3>;
[all …]
H A Dn1sdp.dtsi10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
72 #clock-cells = <0>;
79 #clock-cells = <0>;
86 #address-cells = <2>;
87 #size-cells = <2>;
92 #address-cells = <2>;
93 #interrupt-cells = <3>;
[all …]
H A Dstm32mp131.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
24 nvmem-cells = <&part_number_otp>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
55 #clock-cells = <0>;
[all …]
H A Dmorello-soc.dts19 #address-cells = <2>;
20 #size-cells = <2>;
56 #address-cells = <2>;
57 #size-cells = <0>;
72 #cooling-cells = <2>;
89 #cooling-cells = <2>;
106 #cooling-cells = <2>;
123 #cooling-cells = <2>;
150 #iommu-cells = <1>;
160 #address-cells = <3>;
[all …]
H A Dmorello.dtsi13 #address-cells = <2>;
14 #size-cells = <2>;
22 #address-cells = <2>;
23 #interrupt-cells = <3>;
24 #size-cells = <2>;
59 #mbox-cells = <2>;
69 #address-cells = <1>;
70 #size-cells = <1>;
86 #clock-cells = <0>;
93 #clock-cells = <0>;
[all …]
H A Dcorstone700.dtsi12 #address-cells = <1>;
13 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
36 #interrupt-cells = <3>;
37 #address-cells = <0>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
68 #clock-cells = <0>;
102 #address-cells = <1>;
[all …]
H A Dfvp-ve-Cortex-A5x1.dts17 #address-cells = <2>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
72 #interrupt-cells = <3>;
73 #address-cells = <0>;
85 #clock-cells = <0>;
94 #clock-cells = <0>;
[all …]
H A Dfvp-ve-Cortex-A7x1.dts17 #address-cells = <2>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
37 #address-cells = <2>;
38 #size-cells = <1>;
52 #interrupt-cells = <3>;
53 #address-cells = <0>;
65 #clock-cells = <0>;
80 #interrupt-cells = <1>;
H A Drdaspen.dts16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <2>;
25 #size-cells = <0>;
57 #clock-cells = <0>;
64 #address-cells = <2>;
65 #size-cells = <2>;
71 #address-cells = <1>;
72 #size-cells = <1>;
87 #interrupt-cells = <3>;
[all …]
H A Dfvp-base-psci-common.dtsi19 #address-cells = <2>;
20 #size-cells = <2>;
41 #address-cells = <2>;
42 #size-cells = <0>;
87 #address-cells = <2>;
88 #size-cells = <2>;
109 #address-cells = <1>;
110 #size-cells = <1>;
134 #interrupt-cells = <1>;
140 #address-cells = <3>;
[all …]
H A Dstm32mp157c-ev1-sp_min.dts33 #address-cells = <1>;
34 #size-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
54 #address-cells = <1>;
55 #size-cells = <1>;
H A Dstm32mp157c-ev1.dts34 #address-cells = <1>;
35 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
55 #address-cells = <1>;
56 #size-cells = <1>;
H A Da5ds.dts13 #address-cells = <1>;
14 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
69 #clock-cells = <0>;
76 #clock-cells = <0>;
83 #clock-cells = <0>;
99 #interrupt-cells = <3>;
100 #address-cells = <0>;
127 #address-cells = <1>;
[all …]
H A Dtc-base.dtsi62 #address-cells = <2>;
63 #size-cells = <2>;
70 #address-cells = <1>;
71 #size-cells = <0>;
201 #address-cells = <2>;
202 #size-cells = <2>;
253 #address-cells = <1>;
254 #size-cells = <1>;
268 #mbox-cells = <MHU_MBOX_CELLS>;
278 #mbox-cells = <MHU_MBOX_CELLS>;
[all …]
H A Dfvp-base-gicv3.dtsi14 #interrupt-cells = <3>;
15 #address-cells = <1>;
16 #size-cells = <1>;
29 #msi-cells = <1>;
H A Dfvp-base-gicv5.dtsi15 #interrupt-cells = <3>;
18 #address-cells = <2>;
19 #size-cells = <2>;
29 #address-cells = <2>;
30 #size-cells = <2>;
48 #address-cells = <2>;
49 #size-cells = <2>;
57 #msi-cells = <1>;
68 #address-cells = <0>;
71 #interrupt-cells = <2>;
H A Darm_fpga.dts19 #address-cells = <2>;
20 #size-cells = <2>;
69 #clock-cells = <0>;
76 #clock-cells = <0>;
91 #address-cells = <2>;
92 #interrupt-cells = <3>;
93 #size-cells = <2>;
104 #msi-cells = <1>;
H A Drtsm_ve-motherboard.dtsi15 #clock-cells = <0>;
22 #clock-cells = <0>;
29 #clock-cells = <0>;
51 #clock-cells = <0>;
83 #address-cells = <2>;
84 #size-cells = <1>;
89 #address-cells = <2>; /* SMB chipselect number and offset */
90 #size-cells = <1>;
113 #address-cells = <1>;
114 #size-cells = <1>;
[all …]
H A Drd1ae.dts15 #address-cells = <2>;
16 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
240 #clock-cells = <0>;
247 #clock-cells = <0>;
254 #address-cells = <2>;
255 #size-cells = <2>;
261 #address-cells = <2>;
262 #size-cells = <2>;
[all …]
H A Dmorello-fvp.dts18 #address-cells = <2>;
19 #size-cells = <2>;
55 #address-cells = <2>;
56 #size-cells = <0>;
175 #address-cells = <1>;
176 #size-cells = <0>;
180 #clock-cells = <1>;
187 #clock-cells = <0>;
H A Dn1sdp-multi-chip.dts65 #iommu-cells = <1>;
75 #address-cells = <3>;
76 #size-cells = <2>;
81 #interrupt-cells = <1>;
104 #msi-cells = <1>;
111 #msi-cells = <1>;
/rk3399_ARM-atf/plat/intel/soc/common/fdts/
H A Dagilex5_fdt.dts15 #address-cells = <1>;
16 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
58 #address-cells = <2>;
59 #interrupt-cells = <3>;
60 #size-cells = <1>;
79 #address-cells = <1>;
80 #size-cells = <1>;
/rk3399_ARM-atf/plat/arm/board/fvp/fdts/
H A Dfvp_spmc_optee_sp_manifest.dts18 #address-cells = <2>;
19 #size-cells = <2>;
43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/fdts/
H A Drdv3_spmc_sp_manifest.dts14 #address-cells = <2>;
15 #size-cells = <2>;
39 #address-cells = <0x2>;
40 #size-cells = <0x0>;

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