Merge changes from topic "bk/gicv5_full" into integration

* changes:
feat(fvp): add a GICv5 device tree
refactor(fvp): factor out interrupt information from the dts

refactor(fvp): factor out interrupt information from the dts

The FVP_Base models are all identical. Individual components can be
swapped out without affecting the rest of the system. In order to not

refactor(fvp): factor out interrupt information from the dts

The FVP_Base models are all identical. Individual components can be
swapped out without affecting the rest of the system. In order to not
diverge too much, factor as much common stuff out but leave out
interrupt information so that it can be swapped out.

Change-Id: I4ce5b627c7ca00d98f10eba888cc1bf4d61880a9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(fdts): remove extra members in PCI interrupt-map" into integration

fix(fdts): remove extra members in PCI interrupt-map

The FVP PCI interrupt-map DT entries are wrong and has extra members.
This patch removes the same.

Change-Id: I892cb2e2b8c6a57aec3007518d4f65014

fix(fdts): remove extra members in PCI interrupt-map

The FVP PCI interrupt-map DT entries are wrong and has extra members.
This patch removes the same.

Change-Id: I892cb2e2b8c6a57aec3007518d4f650146934283
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge "feat(fvp): give bootargs on all configs" into integration

feat(fvp): give bootargs on all configs

Linux needs bootargs on all configs. SPM_MM was left as CI wouldn't pass
but the error is unrelated and now works too.

Change-Id: I78874344b5972ae3ff136da5a8

feat(fvp): give bootargs on all configs

Linux needs bootargs on all configs. SPM_MM was left as CI wouldn't pass
but the error is unrelated and now works too.

Change-Id: I78874344b5972ae3ff136da5a8f119d376d53ba2
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(fvp): give bootargs on all configs" into integration

feat(fvp): give bootargs on all configs

Linux needs bootargs with or without RME. Have them always on.

Change-Id: I4e7f582862ba9a0a96c0d6de10d021eed51740d6
Signed-off-by: Boyan Karatotev <boyan.kar

feat(fvp): give bootargs on all configs

Linux needs bootargs with or without RME. Have them always on.

Change-Id: I4e7f582862ba9a0a96c0d6de10d021eed51740d6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS t

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS to 1TB
feat(gpt): statically allocate bitlocks array
chore(gpt): define PPS in platform header files
feat(fvp): allocate L0 GPT at the top of SRAM
feat(fvp): change size of PCIe memory region 2
feat(rmm): add PCIe IO info to Boot manifest
feat(fvp): define single Root region

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feat(fvp): change size of PCIe memory region 2

Change size of PCIe memory region 2 from 256GB
to 3GB to fit in 1TB of GPT PPS.

Change-Id: Ic769bb784dd17d390b54ccef53b7788334373cb4
Signed-off-by: Al

feat(fvp): change size of PCIe memory region 2

Change size of PCIe memory region 2 from 256GB
to 3GB to fit in 1TB of GPT PPS.

Change-Id: Ic769bb784dd17d390b54ccef53b7788334373cb4
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Upda

feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Update RMMD_MANIFEST_VERSION_MINOR from 3 to 4.
- Read PCIe related information from DTB and write it to
Boot manifest.
- Rename structures that used to describe DRAM layout
and now describe both DRAM and PCIe IO memory regions:
- ns_dram_bank -> memory_bank
- ns_dram_info -> memory_info.

Change-Id: Ib75d1af86076f724f5c330074e231f1c2ba8e21d
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge "feat(fvp): add support for virto-net, virtio-9p and virtio-rng" into integration

feat(fvp): add support for virto-net, virtio-9p and virtio-rng

Add virtio-net and virtio-9p devices to the devicetree without the
status set. This ensures that the MMIO frame is set, and it is not
f

feat(fvp): add support for virto-net, virtio-9p and virtio-rng

Add virtio-net and virtio-9p devices to the devicetree without the
status set. This ensures that the MMIO frame is set, and it is not
fatal to start the driver initialisation procedure, which will
typically bail out if it finds zero virtqueues.

Add the virtio-rng device with status disabled. The disabled status
is chosen because the FVP models have only supported this since 2022
and older models would trigger an external abort when trying to access
or probe this MMIO region.

This is included by the fvp-base devicetrees.

Change-Id: Ia0a853533bb5d619a3d415e35b3217ad3a978ada
Signed-off-by: Diego Sueiro <Diego.Sueiro@arm.com>
Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>

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Merge "feat(fvp): add stdout-path" into integration

feat(fvp): add stdout-path

Add stdout-path to the fvp-base devicetree to be passed to BL33 (U-Boot)
and then to the Linux kernel to be compliant to Arm SystemReady IR:
https://developer.arm.com/docu

feat(fvp): add stdout-path

Add stdout-path to the fvp-base devicetree to be passed to BL33 (U-Boot)
and then to the Linux kernel to be compliant to Arm SystemReady IR:
https://developer.arm.com/documentation/DUI1101/2-0/
Configure-U-Boot-for-SystemReady/Adapt-the-Devicetree

This has been tested by booting fvp-base to Linux and ensuring the
console is accessible.

Change-Id: Iae98630f18f735ce344c1158f41f358c2a49eeb6
Signed-off-by: Diego Sueiro <Diego.Sueiro@arm.com>
Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>

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Merge "fix(pmu): switch FVP PMUv3 SPIs to PPI" into integration

fix(pmu): switch FVP PMUv3 SPIs to PPI

FVP PMUv3 SPIs legacy interrupts are only listed for
cluster #0 and are missing for cluster #1.
This patch changes FVP SPIs to PMUv3 PPI as in
arm_fpga.dtsi, m

fix(pmu): switch FVP PMUv3 SPIs to PPI

FVP PMUv3 SPIs legacy interrupts are only listed for
cluster #0 and are missing for cluster #1.
This patch changes FVP SPIs to PMUv3 PPI as in
arm_fpga.dtsi, morello.dtsi and n1sdp.dtsi.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ic624cec09ba932666c746ae1a6a4b78b6decde96

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Merge "feat(rmm): add support for the 2nd DRAM bank" into integration

feat(rmm): add support for the 2nd DRAM bank

This patch adds support for RMM granules allocation
in FVP 2nd DRAM 2GB bank at 0x880000000 base address.
For ENABLE_RME = 1 case it also removes "mem=1G

feat(rmm): add support for the 2nd DRAM bank

This patch adds support for RMM granules allocation
in FVP 2nd DRAM 2GB bank at 0x880000000 base address.
For ENABLE_RME = 1 case it also removes "mem=1G"
Linux kernel command line option in fvp-base-psci-common.dsti
to allow memory layout discovery from the FVP device tree.
FVP parameter 'bp.dram_size' - size of main memory in gigabytes
documented in docs/components/realm-management-extension.rst
is changed from 2 to 4.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I174da4416ad5a8d41bf0ac89f356dba7c0cd3fe7

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Merge changes from topic "fvp_dts_rework" into integration

* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix

Merge changes from topic "fvp_dts_rework" into integration

* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix memtimer subframe addressing
feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel
refactor(fvp): fdts: consolidate GICv2 base FVP DT files
refactor(fvp): fdts: consolidate GICv3 base FVP DT files
feat(fvp): dts: drop 32-bit .dts files
refactor(fvp): fdts: merge motherboard .dtsi files
refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs
fix(fvp): fdts: unify and fix PSCI nodes

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fix(fvp): fdts: Fix idle-states entry method

When firmware implements idle states via PSCI, the value of the DT
entry-method property must be "psci", not "arm,psci".

Fix this to make the CPU descri

fix(fvp): fdts: Fix idle-states entry method

When firmware implements idle states via PSCI, the value of the DT
entry-method property must be "psci", not "arm,psci".

Fix this to make the CPU description binding compliant.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icd1bf704d177368af9b7aab545f47e580791b8cc

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fix(fvp): fdts: fix memtimer subframe addressing

The arm,armv7-timer-mem DT binding documentation demands that the
#size-cells property should be <1> only.

Adjust the value to be <1> and drop the

fix(fvp): fdts: fix memtimer subframe addressing

The arm,armv7-timer-mem DT binding documentation demands that the
#size-cells property should be <1> only.

Adjust the value to be <1> and drop the now needless leading 0 in the
frame's reg property. Convert to #address-cell = <1> on the way.
Also adjust the interrupts property to use the proper GIC macros.

Change-Id: Ia2224663b1e6aaa7cf94af777473641de6a840d2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel

The existing DT files for the base FVP model are having some issues,
that lead to warnings reported by the device tree compiler.

Those

feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel

The existing DT files for the base FVP model are having some issues,
that lead to warnings reported by the device tree compiler.

Those (and many other issues around (updated) DT binding compliance)
were fixed in the Linux kernel tree, so let's sync those files back into
TF-A.
We cannot copy the files "as is" for now, since we rely on certain custom
properties to be added (max-pwr-lvl in the PSCI node, SDEI nodes, etc).

Merge in the changed parts of the Linux kernel DT (from Linux v6.0-rc1),
and rework the base file to allow including the motherboard.dtsi
unchanged. This should make any future update less painful.

As this also affects the FVP VE boards (Cortex-A7 and Cortex-A5), since
they share the motherboard include file, fix them up as well.

Change-Id: I4f74d05e5583747f8849e32f246f74aeec7a9c60
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(fvp): fdts: consolidate GICv3 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally ju

refactor(fvp): fdts: consolidate GICv3 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally just
the interrupt controller node that is different.
To facilitate a unification, refactor the DT include files to explicitly
include a snippet with just the GICv3 description, and a generic base DT
file for the rest. This generic file can then be reused by the GICv2
versions later.

Since we can only have a /memreserve/ entry *before* any DT nodes, move
that line to each file, to allow including the GIC DT file separately.

Change-Id: I9ff357d3fe0ce46e280c30131aeae97a99631512
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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