1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#define AFF 00 10 11#include "fvp-defs.dtsi" 12#undef POST 13#define POST \ 14 }; 15 16/ { 17 compatible = "arm,ffa-core-manifest-1.0"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 attribute { 22 spmc_id = <0x8000>; 23 maj_ver = <0x1>; 24 min_ver = <0x3>; 25 exec_state = <0x0>; 26 load_address = <0x0 0x6000000>; 27 entrypoint = <0x0 0x6000000>; 28 binary_size = <0x80000>; 29 }; 30 31 hypervisor { 32 compatible = "hafnium,hafnium"; 33 vm1 { 34 is_ffa_partition; 35 debug_name = "op-tee"; 36 load_address = <0x6280000>; 37 vcpu_count = <8>; 38 mem_size = <0xd80000>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <0x2>; 44 #size-cells = <0x0>; 45 46 CPU_0 47 48 /* 49 * SPMC (Hafnium) requires secondary core nodes are declared 50 * in descending order. 51 */ 52 CPU_7 53 CPU_6 54 CPU_5 55 CPU_4 56 CPU_3 57 CPU_2 58 CPU_1 59 }; 60 61 memory@6000000 { 62 device_type = "memory"; 63 reg = <0x0 0x6000000 0x0 0x2000000>; /* Trusted DRAM */ 64 }; 65 66 memory@80000000 { 67 device_type = "ns-memory"; 68 reg = <0x0 0x80000000 0x0 0x7c000000>, 69 <0x8 0x80000000 0x1 0x80000000>, 70 <0x00008800 0x80000000 0x0 0x7f000000>; 71 }; 72 73 memory@0 { 74 device_type = "device-memory"; 75 reg = <0x0 0x1c090000 0x0 0x40000>; /* UART */ 76 }; 77}; 78