1*29d1e29dSJit Loon Lim/* 2*29d1e29dSJit Loon Lim * Copyright (c) 2019-2024, Intel Corporation. All rights reserved. 3*29d1e29dSJit Loon Lim * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 4*29d1e29dSJit Loon Lim * 5*29d1e29dSJit Loon Lim * SPDX-License-Identifier: BSD-3-Clause 6*29d1e29dSJit Loon Lim */ 7*29d1e29dSJit Loon Lim 8*29d1e29dSJit Loon Lim/dts-v1/; 9*29d1e29dSJit Loon Lim 10*29d1e29dSJit Loon Lim/ { 11*29d1e29dSJit Loon Lim model = "ALTERA SOCFPGA AGILEX5"; 12*29d1e29dSJit Loon Lim compatible = "arm,altera socfpga-agilex5"; 13*29d1e29dSJit Loon Lim owner = "jit.loon.lim@intel.com"; 14*29d1e29dSJit Loon Lim interrupt-parent = <&gic>; 15*29d1e29dSJit Loon Lim #address-cells = <1>; 16*29d1e29dSJit Loon Lim #size-cells = <1>; 17*29d1e29dSJit Loon Lim 18*29d1e29dSJit Loon Lim psci { 19*29d1e29dSJit Loon Lim compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 20*29d1e29dSJit Loon Lim method = "smc"; 21*29d1e29dSJit Loon Lim 22*29d1e29dSJit Loon Lim cpu_on = <0xdeadc0de>; 23*29d1e29dSJit Loon Lim }; 24*29d1e29dSJit Loon Lim 25*29d1e29dSJit Loon Lim cpus { 26*29d1e29dSJit Loon Lim #address-cells = <1>; 27*29d1e29dSJit Loon Lim #size-cells = <0>; 28*29d1e29dSJit Loon Lim enable-method = "psci"; 29*29d1e29dSJit Loon Lim cpu@0 { 30*29d1e29dSJit Loon Lim device_type = "cpu"; 31*29d1e29dSJit Loon Lim compatible = "arm,cortex-a5"; 32*29d1e29dSJit Loon Lim reg = <0>; 33*29d1e29dSJit Loon Lim }; 34*29d1e29dSJit Loon Lim cpu@1 { 35*29d1e29dSJit Loon Lim device_type = "cpu"; 36*29d1e29dSJit Loon Lim compatible = "arm,cortex-a5"; 37*29d1e29dSJit Loon Lim reg = <1>; 38*29d1e29dSJit Loon Lim }; 39*29d1e29dSJit Loon Lim cpu@2 { 40*29d1e29dSJit Loon Lim device_type = "cpu"; 41*29d1e29dSJit Loon Lim compatible = "arm,cortex-a5"; 42*29d1e29dSJit Loon Lim reg = <2>; 43*29d1e29dSJit Loon Lim }; 44*29d1e29dSJit Loon Lim cpu@3 { 45*29d1e29dSJit Loon Lim device_type = "cpu"; 46*29d1e29dSJit Loon Lim compatible = "arm,cortex-a5"; 47*29d1e29dSJit Loon Lim reg = <3>; 48*29d1e29dSJit Loon Lim }; 49*29d1e29dSJit Loon Lim }; 50*29d1e29dSJit Loon Lim 51*29d1e29dSJit Loon Lim memory@80000000 { 52*29d1e29dSJit Loon Lim device_type = "memory"; 53*29d1e29dSJit Loon Lim reg = <0x80000000 0x90000000>; 54*29d1e29dSJit Loon Lim }; 55*29d1e29dSJit Loon Lim 56*29d1e29dSJit Loon Lim gic: interrupt-controller@2c010000 { 57*29d1e29dSJit Loon Lim compatible = "arm,gic-600", "arm,gic-v3"; 58*29d1e29dSJit Loon Lim #address-cells = <2>; 59*29d1e29dSJit Loon Lim #interrupt-cells = <3>; 60*29d1e29dSJit Loon Lim #size-cells = <1>; 61*29d1e29dSJit Loon Lim #ranges; 62*29d1e29dSJit Loon Lim interrupt-controller; 63*29d1e29dSJit Loon Lim reg = <0x1D000000 0>, /* GICD */ 64*29d1e29dSJit Loon Lim <0x1D060000 0>; /* GICR */ 65*29d1e29dSJit Loon Lim interrupts = <0x1 0x9 0x4>; 66*29d1e29dSJit Loon Lim }; 67*29d1e29dSJit Loon Lim 68*29d1e29dSJit Loon Lim serial0: uart@1a200000 { 69*29d1e29dSJit Loon Lim compatible = "arm,console-16550"; 70*29d1e29dSJit Loon Lim reg = <0x10C02000 0x1000>; 71*29d1e29dSJit Loon Lim interrupt-parent = <&gic>; 72*29d1e29dSJit Loon Lim interrupts = <0 8 0xf04>; 73*29d1e29dSJit Loon Lim clock-frequency = <100000000>; 74*29d1e29dSJit Loon Lim uart-baudrate = <115200>; 75*29d1e29dSJit Loon Lim }; 76*29d1e29dSJit Loon Lim 77*29d1e29dSJit Loon Lim timer0: timer@1a040000 { 78*29d1e29dSJit Loon Lim compatible = "arm,armv7-timer-mem"; 79*29d1e29dSJit Loon Lim #address-cells = <1>; 80*29d1e29dSJit Loon Lim #size-cells = <1>; 81*29d1e29dSJit Loon Lim ranges; 82*29d1e29dSJit Loon Lim reg = <0x1a040000 0x1000>; 83*29d1e29dSJit Loon Lim clock-frequency = <7500000>; 84*29d1e29dSJit Loon Lim 85*29d1e29dSJit Loon Lim frame@1a050000 { 86*29d1e29dSJit Loon Lim frame-number = <0>; 87*29d1e29dSJit Loon Lim interrupts = <0 2 0xf04>; 88*29d1e29dSJit Loon Lim reg = <0x1a050000 0x1000>; 89*29d1e29dSJit Loon Lim }; 90*29d1e29dSJit Loon Lim }; 91*29d1e29dSJit Loon Lim 92*29d1e29dSJit Loon Lim}; 93