Merge "refactor(tc): neaten platform code after TC2 removal" into integration

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes I3d950e72,Id315a8fe,Ib62e6e9b,I1d0475b2 into integration

* changes:
perf(cm): drop ZCR_EL3 saving and some ISBs and replace them with root context
perf(psci): get PMF timestamps wi

Merge changes I3d950e72,Id315a8fe,Ib62e6e9b,I1d0475b2 into integration

* changes:
perf(cm): drop ZCR_EL3 saving and some ISBs and replace them with root context
perf(psci): get PMF timestamps with no cache flushes if possible
perf(amu): greatly simplify AMU context management
perf(mpmm): greatly simplify MPMM enablement

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perf(amu): greatly simplify AMU context management

The current code is incredibly resilient to updates to the spec and
has worked quite well so far. However, recent implementations expose a
weakness

perf(amu): greatly simplify AMU context management

The current code is incredibly resilient to updates to the spec and
has worked quite well so far. However, recent implementations expose a
weakness in that this is rather slow. A large part of it is written in
assembly, making it opaque to the compiler for optimisations. The
future proofness requires reading registers that are effectively
`volatile`, making it even harder for the compiler, as well as adding
lots of implicit barriers, making it hard for the microarchitecutre to
optimise as well.

We can make a few assumptions, checked by a few well placed asserts, and
remove a lot of this burden. For a start, at the moment there are 4
group 0 counters with static assignments. Contexting them is a trivial
affair that doesn't need a loop. Similarly, there can only be up to 16
group 1 counters. Contexting them is a bit harder, but we can do with a
single branch with a falling through switch. If/when both of these
change, we have a pair of asserts and the feature detection mechanism to
guard us against pretending that we support something we don't.

We can drop contexting of the offset registers. They are fully
accessible by EL2 and as such are its responsibility to preserve on
powerdown.

Another small thing we can do, is pass the core_pos into the hook.
The caller already knows which core we're running on, we don't need to
call this non-trivial function again.

Finally, knowing this, we don't really need the auxiliary AMUs to be
described by the device tree. Linux doesn't care at the moment, and any
information we need for EL3 can be neatly placed in a simple array.

All of this, combined with lifting the actual saving out of assembly,
reduces the instructions to save the context from 180 to 40, including a
lot fewer branches. The code is also much shorter and easier to read.

Also propagate to aarch32 so that the two don't diverge too much.

Change-Id: Ib62e6e9ba5be7fb9fb8965c8eee148d5598a5361
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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perf(mpmm): greatly simplify MPMM enablement

MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the s

perf(mpmm): greatly simplify MPMM enablement

MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the same way. Despite that, it is enabled more like an
architectural feature with a top level enable flag. This utilised the
identical implementation.

This duality has left MPMM in an awkward place, where its enablement
should be generic, like an architectural feature, but since it is not,
it should also be core-specific if it ever changes. One choice to do
this has been through the device tree.

This has worked just fine so far, however, recent implementations expose
a weakness in that this is rather slow - the device tree has to be read,
there's a long call stack of functions with many branches, and system
registers are read. In the hot path of PSCI CPU powerdown, this has a
significant and measurable impact. Besides it being a rather large
amount of code that is difficult to understand.

Since MPMM is a microarchitectural feature, its correct placement is in
the reset function. The essence of the current enablement is to write
CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C
enablement with an assembly macro in each CPU's reset function achieves
the same effect with just a single close branch and a grand total of 6
instructions (versus the old 2 branches and 32 instructions).

Having done this, the device tree entry becomes redundant. Should a core
that doesn't support MPMM arise, this can cleanly be handled in the
reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks
mechanisms become obsolete and are removed.

Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "us_tc_trng" into integration

* changes:
feat(tc): get entropy with PSA Crypto API
feat(psa): add interface with RSE for retrieving entropy
fix(psa): guard Crypto APIs

Merge changes from topic "us_tc_trng" into integration

* changes:
feat(tc): get entropy with PSA Crypto API
feat(psa): add interface with RSE for retrieving entropy
fix(psa): guard Crypto APIs with CRYPTO_SUPPORT
feat(tc): enable trng
feat(tc): initialize the RSE communication in earlier phase

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Merge changes I105cd219,Ie870a7f3 into integration

* changes:
feat(tc): add SLC MSC nodes to TC4 DT
refactor(tc): clarify msc0 DT node

feat(tc): enable trng

Enable the trng on the platform, which can be used by other features.
`rng-seed` has been removed and enabled `FEAT_RNG_TRAP` to trap to EL3
when accessing system registers RND

feat(tc): enable trng

Enable the trng on the platform, which can be used by other features.
`rng-seed` has been removed and enabled `FEAT_RNG_TRAP` to trap to EL3
when accessing system registers RNDR and RNDRRS

Change-Id: Ibde39115f285e67d31b14863c75beaf37493deca
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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refactor(tc): clarify msc0 DT node

This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@a

refactor(tc): clarify msc0 DT node

This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4

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Merge changes I58ba6b70,Id463a9dd into integration

* changes:
fix(tc): set console baurate to 38400 for fvp as well
refactor(tc): remove redundant macro UARTCLK_FREQ

refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagd

refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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Merge "fix(tc): replace vencoder with simple panel for kernel > 6.6" into integration

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")

To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.

We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d

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Merge changes I19503ac3,I0fb128a4,I287ab9c3 into integration

* changes:
feat(tc): move flash device to own node
feat(tc): remove static memory used for fwu
fix(tc): correct NS timer frame ID f

Merge changes I19503ac3,I0fb128a4,I287ab9c3 into integration

* changes:
feat(tc): move flash device to own node
feat(tc): remove static memory used for fwu
fix(tc): correct NS timer frame ID for TC

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feat(tc): remove static memory used for fwu

With the updated firmware update implementation in the Trusted Services,
it is no longer needed to carve out static memory. Memory will be
allocated dynam

feat(tc): remove static memory used for fwu

With the updated firmware update implementation in the Trusted Services,
it is no longer needed to carve out static memory. Memory will be
allocated dynamically in U-Boot and shared with the firmware update
secure partition of Trusted Services.

Change-Id: I0fb128a458773236ee10526edfa1116b229e4d6e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME a

Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME and SME2 options for TC4
feat(tc): add new TC4 RoS definitions
feat(tc): add system generic timer register definition for TC4
feat(tc): allow TARGET_VERSION=4
feat(tc): add MHUv3 register addresses for TC4
feat(tc): add device tree binding for TC4

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feat(tc): update DT for Drage GPU

This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC p

feat(tc): update DT for Drage GPU

This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC platforms, this patch appends the interrupt
properties in platform specific DT binding file.

Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3

feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc):

Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc): change GIC DT property 'interrupt-cells' to 4
feat(tc): add NI-Tower PMU node for TC3
feat(tc): setup ni-tower non-secure access for TC3

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fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signe

fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface

feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface.

Change-Id: Ic7a9d9ce927edbce02c7c09470a009dc56247240
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine

feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine
to.

If an interrupt is a PPI, and the node pointed in the 4th cell must be a
subnode of the "ppi-partitions" in the GIC node. For interrupt types
other than PPI, this cell must be zero. This is a preparison for
sequential changes for interrupt partitions, as the first step, it sets
all zeros for the interrupt affinity.

Change-Id: I66490a86a27aad5db6b1a42c2d8e0d042eee46a9
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "ip_smmu" into integration

* changes:
feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
feat(tc): bind SMMU-700 with DPU on TC3
refactor(tc): append binding for SMMU-700

feat(tc): bind SMMU-600 with the DPU on TC3 FPGA

The SMMU 600 is used on TC3 FPGA board with the display device, add the
device tree binding for it.

Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98a

feat(tc): bind SMMU-600 with the DPU on TC3 FPGA

The SMMU 600 is used on TC3 FPGA board with the display device, add the
device tree binding for it.

Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98ae945
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): bind SMMU-700 with DPU on TC3

TC3 adds a new SMMU-700 specifically for the DPU. This is used as the
DPU SMMU instead of the existing SMMU used for the DPU. Update the
device tree to reflec

feat(tc): bind SMMU-700 with DPU on TC3

TC3 adds a new SMMU-700 specifically for the DPU. This is used as the
DPU SMMU instead of the existing SMMU used for the DPU. Update the
device tree to reflect this.

Change-Id: I865140f8f53bceaa8849f6583190b240eeee0539
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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