Merge changes from topic "ahmed-azeem/rdaspen/enhancements" into integration

* changes:
feat(rdaspen): support configurable CPU topology in device tree
feat(rdaspen): add support for configurabl

Merge changes from topic "ahmed-azeem/rdaspen/enhancements" into integration

* changes:
feat(rdaspen): support configurable CPU topology in device tree
feat(rdaspen): add support for configurable platform's CPU topology
feat(rdaspen): scmi gracefully shutdown system
feat(scmi): support graceful system power set
fix(rdaspen): enable CPU feature runtime checking
fix(rdaspen): fix timer bus cells & fix ranges

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feat(rdaspen): support configurable CPU topology in device tree

Adjust the platform's CPU topology in the device tree file based on
the passed build time topology. If no build time topology was
prov

feat(rdaspen): support configurable CPU topology in device tree

Adjust the platform's CPU topology in the device tree file based on
the passed build time topology. If no build time topology was
provided, default topology will be used.

Change-Id: Ied48f27f32d8f7a7df138a98075848c59f7435c0
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

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fix(rdaspen): fix timer bus cells & fix ranges

The timer node is a child bus that should expose frames via a
translating address space per the timer-with-frames binding.
The #size-cells were updated

fix(rdaspen): fix timer bus cells & fix ranges

The timer node is a child bus that should expose frames via a
translating address space per the timer-with-frames binding.
The #size-cells were updated to <1> from <2>, due to a
validation warning when running dt_validate:

/home/root/fdt/fdt: timer@1a810000: #size-cells: 1 was expected

Updating the cell-size to 1 fixes it, and another fix is also
applied to avoid an empty range property.

This models the timer as a proper translating bus:
- Remove clock-frequency since it is already configured in firmware.
- Update #address-cells from <2> to <1>/
- Update #size-cells from <2> to <1>.
- Provide a non-empty ranges mapping the child space at
0x1a810000 over a 0x30000 window.
- Convert frame and reg values to offsets within the child space.

This removes the dtc warnings in dt_validate and aligns with the
dt-schema expectation for the timer-with-frames layout used by
ACS DT validation.

Change-Id: I6deb9ecc0946176b9f9992d80c95db4106eb5820
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add

Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add DSU support
docs(rdaspen): introduce rdaspen docs
feat(rdaspen): enable tbb on rd-aspen platform
feat(gicv3): add GIC-720AE model id
feat(rdaspen): add BL31 for RD-Aspen platform
feat(rdaspen): introduce Arm RD-Aspen platform

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feat(rdaspen): add DSU to the device tree

Update the device tree file to include the AP's DSU clusters'
L3 cache and PMU info.

Change-Id: I0923b1aed1c92f8460370de197a6197de183d7f5
Signed-off-by: Am

feat(rdaspen): add DSU to the device tree

Update the device tree file to include the AP's DSU clusters'
L3 cache and PMU info.

Change-Id: I0923b1aed1c92f8460370de197a6197de183d7f5
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* C

feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* Cortex-A720AE, Armv9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 512 KB is reserved for TF-A
* 4GiB of DRAM in two partitions (extensible)

It also adds:
* FW_CONFIG and HW_CONFIG device trees

Change-Id: I4ba3e4bf1fed8f3640f7eda815607b0a5cab9500
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

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