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Searched refs:GENMASK_32 (Results 1 – 25 of 48) sorted by relevance

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/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_csr_all_cdefines.h1010 #define CSR_MTESTMUXSEL_MASK GENMASK_32(5, 0)
1013 #define CSR_AFORCEDRVCONT_MASK GENMASK_32(3, 0)
1016 #define CSR_AFORCETRICONT_MASK GENMASK_32(3, 0)
1019 #define CSR_ATXIMPEDANCE_MASK GENMASK_32(9, 0)
1021 #define CSR_ADRVSTRENP_MASK GENMASK_32(4, 0)
1023 #define CSR_ADRVSTRENN_MASK GENMASK_32(9, 5)
1026 #define CSR_ATESTPRBSERR_MASK GENMASK_32(3, 0)
1029 #define CSR_ATXSLEWRATE_MASK GENMASK_32(10, 0)
1031 #define CSR_ATXPREP_MASK GENMASK_32(3, 0)
1033 #define CSR_ATXPREN_MASK GENMASK_32(7, 4)
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/rk3399_ARM-atf/drivers/st/usb_dwc3/
H A Dusb_dwc3_regs.h91 #define _DWC3_GSBUSCFG0_DESWRREQINFO_MASK GENMASK_32(19, 16)
93 #define _DWC3_GSBUSCFG0_DATWRREQINFO_MASK GENMASK_32(23, 20)
95 #define _DWC3_GSBUSCFG0_DESRDREQINFO_MASK GENMASK_32(27, 24)
97 #define _DWC3_GSBUSCFG0_DATRDREQINFO_MASK GENMASK_32(31, 28)
101 #define _DWC3_GSBUSCFG1_PIPETRANSLIMIT_MASK GENMASK_32(11, 8)
106 #define _DWC3_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK GENMASK_32(23, 16)
108 #define _DWC3_GTXTHRCFG_USBTXPKTCNT_MASK GENMASK_32(27, 24)
113 #define _DWC3_GRXTHRCFG_RESVISOCOUTSPC_MASK GENMASK_32(12, 0)
115 #define _DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK GENMASK_32(23, 19)
117 #define _DWC3_GRXTHRCFG_USBRXPKTCNT_MASK GENMASK_32(27, 24)
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/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp21_rcc.h673 #define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0)
677 #define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0)
681 #define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0)
687 #define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
689 #define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
694 #define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4)
700 #define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
702 #define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
707 #define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
713 #define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
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H A Dstm32mp25_rcc.h718 #define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0)
722 #define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0)
726 #define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0)
732 #define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
734 #define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
739 #define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4)
745 #define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
747 #define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
752 #define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
758 #define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
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H A Dstm32mp21_pwr.h104 #define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0)
141 #define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8)
146 #define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8)
148 #define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16)
150 #define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24)
156 #define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12)
165 #define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12)
174 #define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12)
183 #define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12)
192 #define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12)
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H A Dstm32mp2_pwr.h133 #define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0)
188 #define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8)
193 #define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8)
195 #define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16)
197 #define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24)
207 #define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12)
216 #define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12)
225 #define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12)
234 #define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12)
243 #define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12)
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H A Dstm32mp2_risaf.h29 #define _RISAF_HWCFGR_CFG1_MASK GENMASK_32(7, 0)
31 #define _RISAF_HWCFGR_CFG2_MASK GENMASK_32(15, 8)
33 #define _RISAF_HWCFGR_CFG3_MASK GENMASK_32(23, 16)
35 #define _RISAF_HWCFGR_CFG4_MASK GENMASK_32(31, 24)
59 #define _RISAF_REG_CFGR_PRIVC_MASK GENMASK_32(23, 16)
64 #define _RISAF_REG_CIDCFGR_RDENC_MASK GENMASK_32(7, 0)
66 #define _RISAF_REG_CIDCFGR_WRENC_MASK GENMASK_32(23, 16)
80 #define DT_RISAF_PRIV_MASK GENMASK_32(15, 8)
82 #define DT_RISAF_READ_MASK GENMASK_32(23, 16)
84 #define DT_RISAF_WRITE_MASK GENMASK_32(31, 24)
H A Dbsec3_reg.h39 #define BSEC_OTPCR_ADDR_MASK GENMASK_32(8, 0)
43 #define BSEC_OTPCR_LASTCID_MASK GENMASK_32(21, 19)
68 #define BSEC_DENR_CP15SDIS_MASK GENMASK_32(14, 13)
71 #define BSEC_DENR_ALL_MSK GENMASK_32(15, 0)
77 #define BSEC_SR_HKWW_MASK GENMASK_32(15, 8)
79 #define BSEC_SR_NVSTATE_MASK GENMASK_32(31, 26)
101 #define BSEC_VERR_MASK GENMASK_32(7, 0)
H A Dstm32mp_rifsc_regs.h30 #define RIFSC_RIMC_ATTRx_MCID_MASK GENMASK_32(6, 4)
40 #define _RIFSC_CIDCFGR_SCID_MASK GENMASK_32(6, 4)
42 #define _RIFSC_CIDCFGR_SEML_MASK GENMASK_32(23, 16)
47 #define _RIFSC_SEMCR_SEMCID_MASK GENMASK_32(6, 4)
H A Dstpmic2.h220 #define LDO4_INPUT_SRC_MASK GENMASK_32(7, 6)
226 #define PWRCTRL_SEL_MASK GENMASK_32(3, 2)
230 #define PREG_MODE_MASK GENMASK_32(2, 1)
233 #define BUCK1_PD_MASK GENMASK_32(1, 0)
234 #define BUCK2_PD_MASK GENMASK_32(3, 2)
235 #define BUCK3_PD_MASK GENMASK_32(5, 4)
236 #define BUCK4_PD_MASK GENMASK_32(7, 6)
244 #define BUCK5_PD_MASK GENMASK_32(1, 0)
245 #define BUCK6_PD_MASK GENMASK_32(3, 2)
246 #define BUCK7_PD_MASK GENMASK_32(5, 4)
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/rk3399_ARM-atf/drivers/nxp/clk/s32cc/include/
H A Ds32cc-clk-regs.h28 #define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET)
32 #define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET)
49 #define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET)
54 #define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U)
59 #define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U)
67 #define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET)
76 #define MC_CGM_MUXn_CSC_SELCTL_MASK GENMASK_32(29U, MC_CGM_MUXn_CSC_SELCTL_OFFSET)
84 #define MC_CGM_MUXn_CSS_SELSTAT_MASK GENMASK_32(29U, MC_CGM_MUXn_CSS_SELSTAT_OFFSET)
90 #define MC_CGM_MUXn_CSS_SWTRG_MASK GENMASK_32(19U, MC_CGM_MUXn_CSS_SWTRG_OFFSET)
100 #define MC_CGM_MUXn_DCm_DIV_MASK GENMASK_32(23U, MC_CGM_MUXn_DCm_DIV_OFFSET)
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/rk3399_ARM-atf/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h36 #define CLK_ID_MASK GENMASK_32(20, 12)
40 #define CLK_DIV_MASK GENMASK_32(10, 5)
44 #define CLK_SEL_MASK GENMASK_32(3, 0)
64 #define FLEX_ID_MASK GENMASK_32(25, 20)
65 #define FLEX_SEL_MASK GENMASK_32(19, 16)
66 #define FLEX_PDIV_MASK GENMASK_32(15, 6)
67 #define FLEX_FDIV_MASK GENMASK_32(5, 0)
H A Dstm32mp25-clksrc.h36 #define CLK_ID_MASK GENMASK_32(20, 12)
40 #define CLK_DIV_MASK GENMASK_32(10, 5)
44 #define CLK_SEL_MASK GENMASK_32(3, 0)
64 #define FLEX_ID_MASK GENMASK_32(25, 20)
65 #define FLEX_SEL_MASK GENMASK_32(19, 16)
66 #define FLEX_PDIV_MASK GENMASK_32(15, 6)
67 #define FLEX_FDIV_MASK GENMASK_32(5, 0)
H A Dstm32mp15-clksrc.h18 #define CMD_MASK GENMASK_32(31, 26)
19 #define CMD_DATA_MASK GENMASK_32(25, 0)
22 #define DIV_ID_MASK GENMASK_32(15, 8)
25 #define DIV_DIVN_MASK GENMASK_32(7, 0)
28 #define MUX_ID_MASK GENMASK_32(11, 4)
31 #define MUX_SEL_MASK GENMASK_32(3, 0)
33 #define CLK_ID_MASK GENMASK_32(19, 11)
37 #define CLK_DIV_MASK GENMASK_32(9, 4)
39 #define CLK_SEL_MASK GENMASK_32(3, 0)
59 #define CLK_ADDR_MASK GENMASK_32(30, 16)
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/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.h26 #define BLKATT_BLKCNT(x) (((x) << 16U) & GENMASK_32(31U, 16U))
27 #define BLKATT_BLKSIZE(x) ((x) & GENMASK_32(12U, 0U))
36 #define XFERTYPE_GET_CMD(x) (((x) & GENMASK_32(29U, 24U)) >> 24U)
62 #define SYSCTRL_CLOCK_MASK GENMASK_32(15U, 4U)
63 #define SYSCTRL_TIMEOUT_MASK GENMASK_32(19U, 16U)
106 #define WMKLV_RD_MASK GENMASK_32(7U, 0U)
107 #define WMKLV_WR_MASK GENMASK_32(23U, 16U)
/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/
H A Ds32cc-ncore.h60 #define NCORE_CAIUID_TYPE GENMASK_32(U(19), U(16))
75 #define NCORE_CSID_NUMSFS_MASK GENMASK_32(U(22), NCORE_CSID_NUMSFS_SHIFT)
82 #define NCORE_CSUID_NUMCMIUS_MASK GENMASK_32(U(29), NCORE_CSUID_NUMCMIUS_SHIFT)
86 #define NCORE_CSUID_NUMDIRUS_MASK GENMASK_32(U(21), NCORE_CSUID_NUMDIRUS_SHIFT)
90 #define NCORE_CSUID_NUMNCBUS_MASK GENMASK_32(U(13), NCORE_CSUID_NUMNCBUS_SHIFT)
/rk3399_ARM-atf/drivers/scmi-msg/
H A Dclock.h101 #define SCMI_CLOCK_CONFIG_SET_ENABLE_MASK GENMASK_32(1, 0)
102 #define SCMI_CLOCK_EXTENDED_CONFIG_SET_TYPE_MASK GENMASK_32(23, 16)
126 #define SCMI_CLOCK_EXTENDED_CONFIG_GET_TYPE_MASK GENMASK_32(7, 0)
187 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK GENMASK_32(31, 16)
193 #define SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK GENMASK_32(11, 0)
H A Dsmt.c55 #define SMT_MSG_ID_MASK GENMASK_32(7, 0)
58 #define SMT_MSG_TYPE_MASK GENMASK_32(9, 8)
61 #define SMT_MSG_PROT_ID_MASK GENMASK_32(17, 10)
/rk3399_ARM-atf/drivers/st/fmc/
H A Dstm32_fmc2_nand.c54 #define FMC2_PCR_PWID_MASK GENMASK_32(5, 4)
60 #define FMC2_PCR_TCLR_MASK GENMASK_32(12, 9)
63 #define FMC2_PCR_TAR_MASK GENMASK_32(16, 13)
66 #define FMC2_PCR_ECCSS_MASK GENMASK_32(19, 17)
75 #define FMC2_PMEM_MEMSET(x) (((x) & GENMASK_32(7, 0)) << 0)
76 #define FMC2_PMEM_MEMWAIT(x) (((x) & GENMASK_32(7, 0)) << 8)
77 #define FMC2_PMEM_MEMHOLD(x) (((x) & GENMASK_32(7, 0)) << 16)
78 #define FMC2_PMEM_MEMHIZ(x) (((x) & GENMASK_32(7, 0)) << 24)
81 #define FMC2_PATT_ATTSET(x) (((x) & GENMASK_32(7, 0)) << 0)
82 #define FMC2_PATT_ATTWAIT(x) (((x) & GENMASK_32(7, 0)) << 8)
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/rk3399_ARM-atf/plat/st/common/
H A Dstm32mp_common.c29 #define BOARD_ID_BOARD_NB_MASK GENMASK_32(31, 16)
31 #define BOARD_ID_VARCPN_MASK GENMASK_32(15, 12)
33 #define BOARD_ID_REVISION_MASK GENMASK_32(11, 8)
35 #define BOARD_ID_VARFG_MASK GENMASK_32(7, 4)
37 #define BOARD_ID_BOM_MASK GENMASK_32(3, 0)
49 #define BOOT_AUTH_MASK GENMASK_32(23, 20)
51 #define BOOT_PART_MASK GENMASK_32(19, 16)
53 #define BOOT_ITF_MASK GENMASK_32(15, 12)
55 #define BOOT_INST_MASK GENMASK_32(11, 8)
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_def.h295 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
435 #define CFG0_OTP_MODE_MASK GENMASK_32(9, 0)
448 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0)
451 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
457 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
474 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
481 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
488 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
497 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dpm_node.h21 #define NODE_CLASS_MASK_BITS GENMASK_32(5, 0)
22 #define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0)
23 #define NODE_TYPE_MASK_BITS GENMASK_32(5, 0)
24 #define NODE_INDEX_MASK_BITS GENMASK_32(13, 0)
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dcm3_system_reset.c68 a3700_gicd_write(GICD_ICENABLER + (i >> 3), GENMASK_32(31, 0)); in a3700_gic_dist_disable_irqs()
90 a3700_gicr_write(proc, GICR_ICENABLER0, GENMASK_32(31, 0)); in a3700_gic_redist_disable_irqs()
119 GENMASK_32(1, 0)); in a3700_io_addr_dec_ack_err_irq()
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dstm32mp2_def.h330 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0)
343 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
350 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
357 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
366 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
392 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0)
/rk3399_ARM-atf/include/lib/
H A Dsmccc.h66 #define SOC_ID_JEP_106_BANK_IDX_MASK GENMASK_32(30, 24)
68 #define SOC_ID_JEP_106_ID_CODE_MASK GENMASK_32(23, 16)
70 #define SOC_ID_IMPL_DEF_MASK GENMASK_32(15, 0)
77 #define SOC_ID_REV_MASK GENMASK_32(30, 0)

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