| #
4f6c787e |
| 09-Jun-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration
* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration
* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family
show more ...
|
| #
2ec3cec5 |
| 24-Jan-2024 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(stm32mp21): add PWR registers file
Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.
Change
feat(stm32mp21): add PWR registers file
Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.
Change-Id: Iedfa764529bcd5119be8e94da7f7b84699e86086
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
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