Lines Matching refs:GENMASK_32
91 #define _DWC3_GSBUSCFG0_DESWRREQINFO_MASK GENMASK_32(19, 16)
93 #define _DWC3_GSBUSCFG0_DATWRREQINFO_MASK GENMASK_32(23, 20)
95 #define _DWC3_GSBUSCFG0_DESRDREQINFO_MASK GENMASK_32(27, 24)
97 #define _DWC3_GSBUSCFG0_DATRDREQINFO_MASK GENMASK_32(31, 28)
101 #define _DWC3_GSBUSCFG1_PIPETRANSLIMIT_MASK GENMASK_32(11, 8)
106 #define _DWC3_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK GENMASK_32(23, 16)
108 #define _DWC3_GTXTHRCFG_USBTXPKTCNT_MASK GENMASK_32(27, 24)
113 #define _DWC3_GRXTHRCFG_RESVISOCOUTSPC_MASK GENMASK_32(12, 0)
115 #define _DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK GENMASK_32(23, 19)
117 #define _DWC3_GRXTHRCFG_USBRXPKTCNT_MASK GENMASK_32(27, 24)
126 #define _DWC3_GCTL_SCALEDOWN_MASK GENMASK_32(5, 4)
128 #define _DWC3_GCTL_RAMCLKSEL_MASK GENMASK_32(7, 6)
134 #define _DWC3_GCTL_PRTCAPDIR_MASK GENMASK_32(13, 12)
136 #define _DWC3_GCTL_FRMSCLDWN_MASK GENMASK_32(15, 14)
141 #define _DWC3_GCTL_PWRDNSCALE_MASK GENMASK_32(31, 19)
145 #define _DWC3_GPMSTS_U2WAKEUP_MASK GENMASK_32(9, 0)
147 #define _DWC3_GPMSTS_U3WAKEUP_MASK GENMASK_32(16, 12)
149 #define _DWC3_GPMSTS_PORTSEL_MASK GENMASK_32(31, 28)
153 #define _DWC3_GSTS_CURMOD_MASK GENMASK_32(1, 0)
163 #define _DWC3_GSTS_CBELT_MASK GENMASK_32(31, 20)
171 #define _DWC3_GUCTL1_L1_SUSP_THRLD_FOR_HOST_MASK GENMASK_32(7, 4)
182 #define _DWC3_GUCTL1_IP_GAP_ADD_ON_MASK GENMASK_32(23, 21)
194 #define _DWC3_GGPIO_GPI_MASK GENMASK_32(15, 0)
196 #define _DWC3_GGPIO_GPO_MASK GENMASK_32(31, 16)
200 #define _DWC3_GUCTL_DTFT_MASK GENMASK_32(8, 0)
202 #define _DWC3_GUCTL_DTCT_MASK GENMASK_32(10, 9)
211 #define _DWC3_GUCTL_REFCLKPER_MASK GENMASK_32(31, 22)
215 #define _DWC3_GPRTBIMAPLO_BINUM1_MASK GENMASK_32(3, 0)
217 #define _DWC3_GPRTBIMAPLO_BINUM2_MASK GENMASK_32(7, 4)
219 #define _DWC3_GPRTBIMAPLO_BINUM3_MASK GENMASK_32(11, 8)
221 #define _DWC3_GPRTBIMAPLO_BINUM4_MASK GENMASK_32(15, 12)
223 #define _DWC3_GPRTBIMAPLO_BINUM5_MASK GENMASK_32(19, 16)
225 #define _DWC3_GPRTBIMAPLO_BINUM6_MASK GENMASK_32(23, 20)
227 #define _DWC3_GPRTBIMAPLO_BINUM7_MASK GENMASK_32(27, 24)
229 #define _DWC3_GPRTBIMAPLO_BINUM8_MASK GENMASK_32(31, 28)
233 #define _DWC3_GPRTBIMAPHI_BINUM9_MASK GENMASK_32(3, 0)
235 #define _DWC3_GPRTBIMAPHI_BINUM10_MASK GENMASK_32(7, 4)
237 #define _DWC3_GPRTBIMAPHI_BINUM11_MASK GENMASK_32(11, 8)
239 #define _DWC3_GPRTBIMAPHI_BINUM12_MASK GENMASK_32(15, 12)
241 #define _DWC3_GPRTBIMAPHI_BINUM13_MASK GENMASK_32(19, 16)
243 #define _DWC3_GPRTBIMAPHI_BINUM14_MASK GENMASK_32(23, 20)
245 #define _DWC3_GPRTBIMAPHI_BINUM15_MASK GENMASK_32(27, 24)
249 #define _DWC3_GHWPARAMS0_GHWPARAMS0_2_0_MASK GENMASK_32(2, 0)
251 #define _DWC3_GHWPARAMS0_GHWPARAMS0_5_3_MASK GENMASK_32(5, 3)
253 #define _DWC3_GHWPARAMS0_GHWPARAMS0_7_6_MASK GENMASK_32(7, 6)
255 #define _DWC3_GHWPARAMS0_GHWPARAMS0_15_8_MASK GENMASK_32(15, 8)
257 #define _DWC3_GHWPARAMS0_GHWPARAMS0_23_16_MASK GENMASK_32(23, 16)
259 #define _DWC3_GHWPARAMS0_GHWPARAMS0_31_24_MASK GENMASK_32(31, 24)
263 #define _DWC3_GHWPARAMS1_GHWPARAMS1_2_0_MASK GENMASK_32(2, 0)
265 #define _DWC3_GHWPARAMS1_GHWPARAMS1_5_3_MASK GENMASK_32(5, 3)
267 #define _DWC3_GHWPARAMS1_GHWPARAMS1_8_6_MASK GENMASK_32(8, 6)
269 #define _DWC3_GHWPARAMS1_GHWPARAMS1_11_9_MASK GENMASK_32(11, 9)
271 #define _DWC3_GHWPARAMS1_GHWPARAMS1_14_12_MASK GENMASK_32(14, 12)
273 #define _DWC3_GHWPARAMS1_GHWPARAMS1_20_15_MASK GENMASK_32(20, 15)
275 #define _DWC3_GHWPARAMS1_GHWPARAMS1_22_21_MASK GENMASK_32(22, 21)
278 #define _DWC3_GHWPARAMS1_GHWPARAMS1_25_24_MASK GENMASK_32(25, 24)
288 #define _DWC3_GHWPARAMS3_GHWPARAMS3_1_0_MASK GENMASK_32(1, 0)
290 #define _DWC3_GHWPARAMS3_GHWPARAMS3_3_2_MASK GENMASK_32(3, 2)
292 #define _DWC3_GHWPARAMS3_GHWPARAMS3_5_4_MASK GENMASK_32(5, 4)
294 #define _DWC3_GHWPARAMS3_GHWPARAMS3_7_6_MASK GENMASK_32(7, 6)
296 #define _DWC3_GHWPARAMS3_GHWPARAMS3_9_8_MASK GENMASK_32(9, 8)
300 #define _DWC3_GHWPARAMS3_GHWPARAMS3_17_12_MASK GENMASK_32(17, 12)
302 #define _DWC3_GHWPARAMS3_GHWPARAMS3_22_18_MASK GENMASK_32(22, 18)
304 #define _DWC3_GHWPARAMS3_GHWPARAMS3_30_23_MASK GENMASK_32(30, 23)
309 #define _DWC3_GHWPARAMS4_GHWPARAMS4_5_0_MASK GENMASK_32(5, 0)
312 #define _DWC3_GHWPARAMS4_GHWPARAMS4_8_7_MASK GENMASK_32(8, 7)
314 #define _DWC3_GHWPARAMS4_GHWPARAMS4_10_9_MASK GENMASK_32(10, 9)
318 #define _DWC3_GHWPARAMS4_GHWPARAMS4_16_13_MASK GENMASK_32(16, 13)
320 #define _DWC3_GHWPARAMS4_GHWPARAMS4_20_17_MASK GENMASK_32(20, 17)
325 #define _DWC3_GHWPARAMS4_GHWPARAMS4_27_24_MASK GENMASK_32(27, 24)
327 #define _DWC3_GHWPARAMS4_GHWPARAMS4_31_28_MASK GENMASK_32(31, 28)
331 #define _DWC3_GHWPARAMS5_GHWPARAMS5_3_0_MASK GENMASK_32(3, 0)
333 #define _DWC3_GHWPARAMS5_GHWPARAMS5_9_4_MASK GENMASK_32(9, 4)
335 #define _DWC3_GHWPARAMS5_GHWPARAMS5_15_10_MASK GENMASK_32(15, 10)
337 #define _DWC3_GHWPARAMS5_GHWPARAMS5_21_16_MASK GENMASK_32(21, 16)
339 #define _DWC3_GHWPARAMS5_GHWPARAMS5_27_22_MASK GENMASK_32(27, 22)
341 #define _DWC3_GHWPARAMS5_GHWPARAMS5_31_28_MASK GENMASK_32(31, 28)
345 #define _DWC3_GHWPARAMS6_GHWPARAMS6_5_0_MASK GENMASK_32(5, 0)
349 #define _DWC3_GHWPARAMS6_GHWPARAMS6_9_8_MASK GENMASK_32(9, 8)
357 #define _DWC3_GHWPARAMS6_GHWPARAMS6_31_16_MASK GENMASK_32(31, 16)
361 #define _DWC3_GHWPARAMS7_GHWPARAMS7_15_0_MASK GENMASK_32(15, 0)
363 #define _DWC3_GHWPARAMS7_GHWPARAMS7_31_16_MASK GENMASK_32(31, 16)
367 #define _DWC3_GDBGFIFOSPACE_FIFO_QUEUE_SELECT_MASK GENMASK_32(8, 0)
369 #define _DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE_MASK GENMASK_32(31, 16)
376 #define _DWC3_GDBGLTSSM_LTDBCLKSTATE_MASK GENMASK_32(5, 3)
378 #define _DWC3_GDBGLTSSM_TXDEEMPHASIS_MASK GENMASK_32(7, 6)
381 #define _DWC3_GDBGLTSSM_POWERDOWN_MASK GENMASK_32(10, 9)
383 #define _DWC3_GDBGLTSSM_LTDBPHYCMDSTATE_MASK GENMASK_32(13, 11)
389 #define _DWC3_GDBGLTSSM_LTDBSUBSTATE_MASK GENMASK_32(21, 18)
391 #define _DWC3_GDBGLTSSM_LTDBLINKSTATE_MASK GENMASK_32(25, 22)
400 #define _DWC3_GDBGLNMCC_LNMCC_BERC_MASK GENMASK_32(8, 0)
404 #define _DWC3_GDBGBMU_BMU_CCU_MASK GENMASK_32(3, 0)
406 #define _DWC3_GDBGBMU_BMU_DCU_MASK GENMASK_32(7, 4)
408 #define _DWC3_GDBGBMU_BMU_BCU_MASK GENMASK_32(31, 8)
412 #define _DWC3_GDBGLSPMUX_HST_HOSTSELECT_MASK GENMASK_32(13, 0)
414 #define _DWC3_GDBGLSPMUX_HST_LOGIC_ANALYZER_TRACE_MASK GENMASK_32(23, 16)
418 #define _DWC3_GPRTBIMAP_HSLO_BINUM1_MASK GENMASK_32(3, 0)
420 #define _DWC3_GPRTBIMAP_HSLO_BINUM2_MASK GENMASK_32(7, 4)
422 #define _DWC3_GPRTBIMAP_HSLO_BINUM3_MASK GENMASK_32(11, 8)
424 #define _DWC3_GPRTBIMAP_HSLO_BINUM4_MASK GENMASK_32(15, 12)
426 #define _DWC3_GPRTBIMAP_HSLO_BINUM5_MASK GENMASK_32(19, 16)
428 #define _DWC3_GPRTBIMAP_HSLO_BINUM6_MASK GENMASK_32(23, 20)
430 #define _DWC3_GPRTBIMAP_HSLO_BINUM7_MASK GENMASK_32(27, 24)
432 #define _DWC3_GPRTBIMAP_HSLO_BINUM8_MASK GENMASK_32(31, 28)
436 #define _DWC3_GPRTBIMAP_HSHI_BINUM9_MASK GENMASK_32(3, 0)
438 #define _DWC3_GPRTBIMAP_HSHI_BINUM10_MASK GENMASK_32(7, 4)
440 #define _DWC3_GPRTBIMAP_HSHI_BINUM11_MASK GENMASK_32(11, 8)
442 #define _DWC3_GPRTBIMAP_HSHI_BINUM12_MASK GENMASK_32(15, 12)
444 #define _DWC3_GPRTBIMAP_HSHI_BINUM13_MASK GENMASK_32(19, 16)
446 #define _DWC3_GPRTBIMAP_HSHI_BINUM14_MASK GENMASK_32(23, 20)
448 #define _DWC3_GPRTBIMAP_HSHI_BINUM15_MASK GENMASK_32(27, 24)
452 #define _DWC3_GPRTBIMAP_FSLO_BINUM1_MASK GENMASK_32(3, 0)
454 #define _DWC3_GPRTBIMAP_FSLO_BINUM2_MASK GENMASK_32(7, 4)
456 #define _DWC3_GPRTBIMAP_FSLO_BINUM3_MASK GENMASK_32(11, 8)
458 #define _DWC3_GPRTBIMAP_FSLO_BINUM4_MASK GENMASK_32(15, 12)
460 #define _DWC3_GPRTBIMAP_FSLO_BINUM5_MASK GENMASK_32(19, 16)
462 #define _DWC3_GPRTBIMAP_FSLO_BINUM6_MASK GENMASK_32(23, 20)
464 #define _DWC3_GPRTBIMAP_FSLO_BINUM7_MASK GENMASK_32(27, 24)
466 #define _DWC3_GPRTBIMAP_FSLO_BINUM8_MASK GENMASK_32(31, 28)
470 #define _DWC3_GPRTBIMAP_FSHI_BINUM9_MASK GENMASK_32(3, 0)
472 #define _DWC3_GPRTBIMAP_FSHI_BINUM10_MASK GENMASK_32(7, 4)
474 #define _DWC3_GPRTBIMAP_FSHI_BINUM11_MASK GENMASK_32(11, 8)
476 #define _DWC3_GPRTBIMAP_FSHI_BINUM12_MASK GENMASK_32(15, 12)
478 #define _DWC3_GPRTBIMAP_FSHI_BINUM13_MASK GENMASK_32(19, 16)
480 #define _DWC3_GPRTBIMAP_FSHI_BINUM14_MASK GENMASK_32(23, 20)
482 #define _DWC3_GPRTBIMAP_FSHI_BINUM15_MASK GENMASK_32(27, 24)
486 #define _DWC3_GUCTL2_TXPINGDURATION_MASK GENMASK_32(4, 0)
488 #define _DWC3_GUCTL2_RXPINGDURATION_MASK GENMASK_32(10, 5)
493 #define _DWC3_GUCTL2_NOLOWPWRDUR_MASK GENMASK_32(18, 15)
495 #define _DWC3_GUCTL2_EN_HP_PM_TIMER_MASK GENMASK_32(25, 19)
499 #define _DWC3_GTXFIFOPRIDEV_GTXFIFOPRIDEV_MASK GENMASK_32(11, 0)
503 #define _DWC3_GTXFIFOPRIHST_GTXFIFOPRIHST_MASK GENMASK_32(2, 0)
507 #define _DWC3_GRXFIFOPRIHST_GRXFIFOPRIHST_MASK GENMASK_32(2, 0)
511 #define _DWC3_GDMAHLRATIO_HSTTXFIFO_MASK GENMASK_32(4, 0)
513 #define _DWC3_GDMAHLRATIO_HSTRXFIFO_MASK GENMASK_32(12, 8)
517 #define _DWC3_GFLADJ_GFLADJ_30MHZ_MASK GENMASK_32(5, 0)
520 #define _DWC3_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK GENMASK_32(21, 8)
523 #define _DWC3_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_MASK GENMASK_32(30, 24)
528 #define _DWC3_GUSB2PHYCFG_TOUTCAL_MASK GENMASK_32(2, 0)
537 #define _DWC3_GUSB2PHYCFG_USBTRDTIM_MASK GENMASK_32(13, 10)
542 #define _DWC3_GUSB2PHYCFG_LSIPD_MASK GENMASK_32(21, 19)
544 #define _DWC3_GUSB2PHYCFG_LSTRD_MASK GENMASK_32(24, 22)
547 #define _DWC3_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_MASK GENMASK_32(28, 27)
554 #define _DWC3_GUSB2PHYACC_ULPI_REGDATA_MASK GENMASK_32(7, 0)
556 #define _DWC3_GUSB2PHYACC_ULPI_EXTREGADDR_MASK GENMASK_32(15, 8)
558 #define _DWC3_GUSB2PHYACC_ULPI_REGADDR_MASK GENMASK_32(21, 16)
568 #define _DWC3_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_MASK GENMASK_32(2, 1)
570 #define _DWC3_GUSB3PIPECTL_TX_MARGIN_MASK GENMASK_32(5, 3)
581 #define _DWC3_GUSB3PIPECTL_DATWIDTH_MASK GENMASK_32(16, 15)
585 #define _DWC3_GUSB3PIPECTL_DELAYP1P2P3_MASK GENMASK_32(21, 19)
599 #define _DWC3_GTXFIFOSIZ0_TXFDEP_N_MASK GENMASK_32(15, 0)
601 #define _DWC3_GTXFIFOSIZ0_TXFSTADDR_N_MASK GENMASK_32(31, 16)
605 #define _DWC3_GTXFIFOSIZ1_TXFDEP_N_MASK GENMASK_32(15, 0)
607 #define _DWC3_GTXFIFOSIZ1_TXFSTADDR_N_MASK GENMASK_32(31, 16)
611 #define _DWC3_GTXFIFOSIZ2_TXFDEP_N_MASK GENMASK_32(15, 0)
613 #define _DWC3_GTXFIFOSIZ2_TXFSTADDR_N_MASK GENMASK_32(31, 16)
617 #define _DWC3_GTXFIFOSIZ3_TXFDEP_N_MASK GENMASK_32(15, 0)
619 #define _DWC3_GTXFIFOSIZ3_TXFSTADDR_N_MASK GENMASK_32(31, 16)
623 #define _DWC3_GTXFIFOSIZ4_TXFDEP_N_MASK GENMASK_32(15, 0)
625 #define _DWC3_GTXFIFOSIZ4_TXFSTADDR_N_MASK GENMASK_32(31, 16)
629 #define _DWC3_GTXFIFOSIZ5_TXFDEP_N_MASK GENMASK_32(15, 0)
631 #define _DWC3_GTXFIFOSIZ5_TXFSTADDR_N_MASK GENMASK_32(31, 16)
635 #define _DWC3_GTXFIFOSIZ6_TXFDEP_N_MASK GENMASK_32(15, 0)
637 #define _DWC3_GTXFIFOSIZ6_TXFSTADDR_N_MASK GENMASK_32(31, 16)
641 #define _DWC3_GTXFIFOSIZ7_TXFDEP_N_MASK GENMASK_32(15, 0)
643 #define _DWC3_GTXFIFOSIZ7_TXFSTADDR_N_MASK GENMASK_32(31, 16)
647 #define _DWC3_GTXFIFOSIZ8_TXFDEP_N_MASK GENMASK_32(15, 0)
649 #define _DWC3_GTXFIFOSIZ8_TXFSTADDR_N_MASK GENMASK_32(31, 16)
653 #define _DWC3_GTXFIFOSIZ9_TXFDEP_N_MASK GENMASK_32(15, 0)
655 #define _DWC3_GTXFIFOSIZ9_TXFSTADDR_N_MASK GENMASK_32(31, 16)
659 #define _DWC3_GTXFIFOSIZ10_TXFDEP_N_MASK GENMASK_32(15, 0)
661 #define _DWC3_GTXFIFOSIZ10_TXFSTADDR_N_MASK GENMASK_32(31, 16)
665 #define _DWC3_GTXFIFOSIZ11_TXFDEP_N_MASK GENMASK_32(15, 0)
667 #define _DWC3_GTXFIFOSIZ11_TXFSTADDR_N_MASK GENMASK_32(31, 16)
671 #define _DWC3_GRXFIFOSIZ0_RXFDEP_N_MASK GENMASK_32(15, 0)
673 #define _DWC3_GRXFIFOSIZ0_RXFSTADDR_N_MASK GENMASK_32(31, 16)
677 #define _DWC3_GRXFIFOSIZ1_RXFDEP_N_MASK GENMASK_32(15, 0)
679 #define _DWC3_GRXFIFOSIZ1_RXFSTADDR_N_MASK GENMASK_32(31, 16)
683 #define _DWC3_GRXFIFOSIZ2_RXFDEP_N_MASK GENMASK_32(15, 0)
685 #define _DWC3_GRXFIFOSIZ2_RXFSTADDR_N_MASK GENMASK_32(31, 16)
689 #define _DWC3_GEVNTSIZ_EVENTSIZ_MASK GENMASK_32(15, 0)
694 #define _DWC3_GEVNTCOUNT_EVNTCOUNT_MASK GENMASK_32(15, 0)
715 #define _DWC3_DCFG_DEVSPD_MASK GENMASK_32(2, 0)
717 #define _DWC3_DCFG_DEVADDR_MASK GENMASK_32(9, 3)
719 #define _DWC3_DCFG_INTRNUM_MASK GENMASK_32(16, 12)
721 #define _DWC3_DCFG_NUMP_MASK GENMASK_32(21, 17)
727 #define _DWC3_DCTL_TSTCTL_MASK GENMASK_32(4, 1)
729 #define _DWC3_DCTL_ULSTCHNGREQ_MASK GENMASK_32(8, 5)
739 #define _DWC3_DCTL_LPM_NYET_THRES_MASK GENMASK_32(23, 20)
741 #define _DWC3_DCTL_HIRDTHRES_MASK GENMASK_32(28, 24)
764 #define _DWC3_DSTS_CONNECTSPD_MASK GENMASK_32(2, 0)
766 #define _DWC3_DSTS_SOFFN_MASK GENMASK_32(16, 3)
769 #define _DWC3_DSTS_USBLNKST_MASK GENMASK_32(21, 18)
779 #define _DWC3_DGCMD_CMDTYP_MASK GENMASK_32(7, 0)
783 #define _DWC3_DGCMD_CMDSTATUS_MASK GENMASK_32(15, 12)
787 #define _DWC3_DEPCMD_CMDTYP_MASK GENMASK_32(3, 0)
792 #define _DWC3_DEPCMD_CMDSTATUS_MASK GENMASK_32(15, 12)
794 #define _DWC3_DEPCMD_COMMANDPARAM_MASK GENMASK_32(31, 16)
798 #define _DWC3_DEV_IMOD_DEVICE_IMODI_MASK GENMASK_32(15, 0)
800 #define _DWC3_DEV_IMOD_DEVICE_IMODC_MASK GENMASK_32(31, 16)
815 #define _DWC3_BCEVT_MULTVALIDBC_MASK GENMASK_32(4, 0)
835 #define _DWC3_CAPLENGTH_CAPLENGTH_MASK GENMASK_32(7, 0)
837 #define _DWC3_CAPLENGTH_HCIVERSION_MASK GENMASK_32(31, 16)
841 #define _DWC3_HCSPARAMS1_MAXSLOTS_MASK GENMASK_32(7, 0)
843 #define _DWC3_HCSPARAMS1_MAXINTRS_MASK GENMASK_32(18, 8)
845 #define _DWC3_HCSPARAMS1_MAXPORTS_MASK GENMASK_32(31, 24)
849 #define _DWC3_HCSPARAMS2_IST_MASK GENMASK_32(3, 0)
851 #define _DWC3_HCSPARAMS2_ERSTMAX_MASK GENMASK_32(7, 4)
853 #define _DWC3_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_MASK GENMASK_32(25, 21)
856 #define _DWC3_HCSPARAMS2_MAXSCRATCHPADBUFS_MASK GENMASK_32(31, 27)
860 #define _DWC3_HCSPARAMS3_U1_DEVICE_EXIT_LAT_MASK GENMASK_32(7, 0)
862 #define _DWC3_HCSPARAMS3_U2_DEVICE_EXIT_LAT_MASK GENMASK_32(31, 16)
878 #define _DWC3_HCCPARAMS1_MAXPSASIZE_MASK GENMASK_32(15, 12)
880 #define _DWC3_HCCPARAMS1_XECP_MASK GENMASK_32(31, 16)
884 #define _DWC3_DBOFF_DOORBELL_ARRAY_OFFSET_MASK GENMASK_32(31, 2)
888 #define _DWC3_RTSOFF_RUNTIME_REG_SPACE_OFFSET_MASK GENMASK_32(31, 5)
936 #define _DWC3_PAGESIZE_PAGE_SIZE_MASK GENMASK_32(15, 0)
940 #define _DWC3_DNCTRL_N0_N15_MASK GENMASK_32(15, 0)
948 #define _DWC3_CRCR_LO_CMD_RING_PNTR_MASK GENMASK_32(31, 6)
952 #define _DWC3_DCBAAP_LO_DEVICE_CONTEXT_BAAP_MASK GENMASK_32(31, 6)
956 #define _DWC3_CONFIG_MAXSLOTSEN_MASK GENMASK_32(7, 0)
978 #define _DWC3_PORTSC_20_PLS_MASK GENMASK_32(8, 5)
981 #define _DWC3_PORTSC_20_PORTSPEED_MASK GENMASK_32(13, 10)
983 #define _DWC3_PORTSC_20_PIC_MASK GENMASK_32(15, 14)
998 #define _DWC3_PORTPMSC_20_L1S_MASK GENMASK_32(2, 0)
1001 #define _DWC3_PORTPMSC_20_HIRD_MASK GENMASK_32(7, 4)
1003 #define _DWC3_PORTPMSC_20_L1DSLOT_MASK GENMASK_32(15, 8)
1006 #define _DWC3_PORTPMSC_20_PRTTSTCTRL_MASK GENMASK_32(31, 28)
1010 #define _DWC3_PORTHLPMC_20_HIRDM_MASK GENMASK_32(1, 0)
1012 #define _DWC3_PORTHLPMC_20_L1_TIMEOUT_MASK GENMASK_32(9, 2)
1014 #define _DWC3_PORTHLPMC_20_HIRDD_MASK GENMASK_32(13, 10)
1022 #define _DWC3_PORTSC_30_PLS_MASK GENMASK_32(8, 5)
1025 #define _DWC3_PORTSC_30_PORTSPEED_MASK GENMASK_32(13, 10)
1027 #define _DWC3_PORTSC_30_PIC_MASK GENMASK_32(15, 14)
1045 #define _DWC3_PORTPMSC_30_U1_TIMEOUT_MASK GENMASK_32(7, 0)
1047 #define _DWC3_PORTPMSC_30_U2_TIMEOUT_MASK GENMASK_32(15, 8)
1052 #define _DWC3_PORTLI_30_LINK_ERROR_COUNT_MASK GENMASK_32(15, 0)
1061 #define _DWC3_MFINDEX_MICROFRAME_INDEX_MASK GENMASK_32(13, 0)
1080 #define _DWC3_IMOD_IMODI_MASK GENMASK_32(15, 0)
1082 #define _DWC3_IMOD_IMODC_MASK GENMASK_32(31, 16)
1086 #define _DWC3_ERSTSZ_ERS_TABLE_SIZE_MASK GENMASK_32(15, 0)
1090 #define _DWC3_ERSTBA_LO_ERS_TABLE_BAR_MASK GENMASK_32(31, 6)
1094 #define _DWC3_ERDP_LO_DESI_MASK GENMASK_32(2, 0)
1097 #define _DWC3_ERDP_LO_ERD_PNTR_MASK GENMASK_32(31, 4)
1106 #define _DWC3_DB_DB_TARGET_MASK GENMASK_32(7, 0)
1108 #define _DWC3_DB_DB_STREAM_ID_MASK GENMASK_32(31, 16)
1138 #define _DWC3_USBLEGSUP_CAPABILITY_ID_MASK GENMASK_32(7, 0)
1140 #define _DWC3_USBLEGSUP_NEXT_CAPABILITY_POINTER_MASK GENMASK_32(15, 8)
1166 #define _DWC3_SUPTPRT2_DW0_CAPABILITY_ID_MASK GENMASK_32(7, 0)
1168 #define _DWC3_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_MASK GENMASK_32(15, 8)
1170 #define _DWC3_SUPTPRT2_DW0_MINOR_REVISION_MASK GENMASK_32(23, 16)
1172 #define _DWC3_SUPTPRT2_DW0_MAJOR_REVISION_MASK GENMASK_32(31, 24)
1176 #define _DWC3_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_MASK GENMASK_32(7, 0)
1178 #define _DWC3_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_MASK GENMASK_32(15, 8)
1184 #define _DWC3_SUPTPRT2_DW2_MHD_MASK GENMASK_32(27, 25)
1186 #define _DWC3_SUPTPRT2_DW2_PSIC_MASK GENMASK_32(31, 28)
1190 #define _DWC3_SUPTPRT2_DW3_PROTCL_SLT_TY_MASK GENMASK_32(4, 0)
1202 #define _DWC3_SUPTPRT3_DW0_CAPABILITY_ID_MASK GENMASK_32(7, 0)
1204 #define _DWC3_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_MASK GENMASK_32(15, 8)
1206 #define _DWC3_SUPTPRT3_DW0_MINOR_REVISION_MASK GENMASK_32(23, 16)
1208 #define _DWC3_SUPTPRT3_DW0_MAJOR_REVISION_MASK GENMASK_32(31, 24)
1212 #define _DWC3_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_MASK GENMASK_32(7, 0)
1214 #define _DWC3_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_MASK GENMASK_32(15, 8)
1216 #define _DWC3_SUPTPRT3_DW2_MHD_MASK GENMASK_32(27, 25)
1218 #define _DWC3_SUPTPRT3_DW2_PSIC_MASK GENMASK_32(31, 28)
1222 #define _DWC3_SUPTPRT3_DW3_PROTCL_SLT_TY_MASK GENMASK_32(4, 0)