History log of /rk3399_ARM-atf/plat/marvell/armada/a3k/common/cm3_system_reset.c (Results 1 – 6 of 6)
Revision Date Author Comments
# 517b7f96 13-Jun-2024 Manish Pandey <manish.pandey2@arm.com>

Merge "fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor" into integration


# 5993af45 11-Apr-2024 Marek Behún <marek.behun@nic.cz>

fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor

Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via th

fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor

Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via the Cortex-M3 secure
coprocessor.

Recall that Turris MOX has a HW bug wherein a SoC reset initiated by
writing the magic value to the North Bridge Warm Reset register may
randomly freeze the board.

Back in 2021 we introduced the CM3_SYSTEM_RESET build option for the
Armada 3700 platform, which, when enabled, adds code to the PSCI reset
handler so that the SoC reset is done by requesting the firmware in the
Cortex-M3 secure coprocessor to do it, instead of writing the Warm Reset
register.

The secure coprocessor firmware tried various things to put the board
into a state where the SoC reset circuit would work correctly. This
managed to fix the issue for some boards, but not for all of them.

Another considered method to overcome this issue was to reset all the
SoC peripheral controllers one by one by writing to specific registers,
instead of triggering the SoC reset circuit via the Warm Reset register.
This method was not used because until now, there was one peripheral
that I could not find a way how to reset properly: the Generic Interrupt
Controller (GIC).

After 3 years I have finally found a way how to reset the GIC, and it
needs to be done by the main processor, before the secure coprocessor
resets the main processor.

Change-Id: Icc23251ef97738b6b48af514d5118440ec21cdd7
Signed-off-by: Marek Behún <marek.behun@nic.cz>

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# 02c6f366 16-Mar-2022 Manish Pandey <manish.pandey2@arm.com>

Merge "fix(a3k): change fatal error to warning when CM3 reset is not implemented" into integration


# 30cdbe70 12-Mar-2022 Pali Rohár <pali@kernel.org>

fix(a3k): change fatal error to warning when CM3 reset is not implemented

This allows TF-A's a3700_system_reset() function to try Warm reset
method when CM3 reset method is not implemented by WTMI f

fix(a3k): change fatal error to warning when CM3 reset is not implemented

This allows TF-A's a3700_system_reset() function to try Warm reset
method when CM3 reset method is not implemented by WTMI firmware.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I7303197373e1a8ca5a44ba0b1e90b48855d6c0c3

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# fde125cb 06-Jan-2021 Manish Pandey <manish.pandey2@arm.com>

Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration


# d9243f26 05-Jan-2021 Marek Behún <marek.behun@nic.cz>

plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor

Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset h

plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor

Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)

The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f

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