drivers/st/stm32mp2_pwr.h

133 #define PWR_CR10_RETRBSEN_MASK			GENMASK_32(1, 0)
188 #define PWR_D1CR_POPL_D1_MASK			GENMASK_32(12, 8)
193 #define PWR_D2CR_POPL_D2_MASK			GENMASK_32(12, 8)
195 #define PWR_D2CR_LPLVDLY_D2_MASK		GENMASK_32(18, 16)
197 #define PWR_D2CR_PODH_D2_MASK			GENMASK_32(27, 24)
207 #define PWR_WKUPCR1_WKUPPUPD_MASK		GENMASK_32(13, 12)
216 #define PWR_WKUPCR2_WKUPPUPD_MASK		GENMASK_32(13, 12)
225 #define PWR_WKUPCR3_WKUPPUPD_MASK		GENMASK_32(13, 12)
234 #define PWR_WKUPCR4_WKUPPUPD_MASK		GENMASK_32(13, 12)
243 #define PWR_WKUPCR5_WKUPPUPD_MASK		GENMASK_32(13, 12)
252 #define PWR_WKUPCR6_WKUPPUPD_MASK		GENMASK_32(13, 12)
281 #define PWR_R0CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
286 #define PWR_R1CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
291 #define PWR_R2CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
296 #define PWR_R3CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
301 #define PWR_R4CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
306 #define PWR_R5CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
311 #define PWR_R6CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
333 #define PWR_WIO1CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
346 #define PWR_WIO1SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
352 #define PWR_WIO2CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
365 #define PWR_WIO2SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
371 #define PWR_WIO3CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
384 #define PWR_WIO3SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
390 #define PWR_WIO4CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
403 #define PWR_WIO4SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
409 #define PWR_WIO5CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
422 #define PWR_WIO5SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
428 #define PWR_WIO6CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
441 #define PWR_WIO6SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
446 #define PWR_CPU1D1SR_CSTATE_MASK		GENMASK_32(3, 2)
448 #define PWR_CPU1D1SR_DSTATE_MASK		GENMASK_32(10, 8)
454 #define PWR_CPU2D2SR_CSTATE_MASK		GENMASK_32(3, 2)
456 #define PWR_CPU2D2SR_DSTATE_MASK		GENMASK_32(10, 8)
460 #define PWR_CPU3D3SR_CSTATE_MASK		GENMASK_32(3, 2)
462 #define PWR_CPU3D3SR_DSTATE_MASK		GENMASK_32(10, 8)
473 #define PWR_VERR_MINREV_MASK			GENMASK_32(3, 0)
475 #define PWR_VERR_MAJREV_MASK			GENMASK_32(7, 4)