drivers/st/stm32mp21_pwr.h

104 #define PWR_CR10_RETRBSEN_MASK			GENMASK_32(1, 0)
141 #define PWR_D1CR_POPL_D1_MASK			GENMASK_32(12, 8)
146 #define PWR_D2CR_POPL_D2_MASK			GENMASK_32(12, 8)
148 #define PWR_D2CR_LPLVDLY_D2_MASK		GENMASK_32(18, 16)
150 #define PWR_D2CR_PODH_D2_MASK			GENMASK_32(27, 24)
156 #define PWR_WKUPCR1_WKUPPUPD_MASK		GENMASK_32(13, 12)
165 #define PWR_WKUPCR2_WKUPPUPD_MASK		GENMASK_32(13, 12)
174 #define PWR_WKUPCR3_WKUPPUPD_MASK		GENMASK_32(13, 12)
183 #define PWR_WKUPCR4_WKUPPUPD_MASK		GENMASK_32(13, 12)
192 #define PWR_WKUPCR5_WKUPPUPD_MASK		GENMASK_32(13, 12)
201 #define PWR_WKUPCR6_WKUPPUPD_MASK		GENMASK_32(13, 12)
227 #define PWR_R0CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
232 #define PWR_R1CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
237 #define PWR_R2CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
242 #define PWR_R3CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
247 #define PWR_R4CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
252 #define PWR_R5CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
257 #define PWR_R6CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
279 #define PWR_WIO1CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
292 #define PWR_WIO1SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
298 #define PWR_WIO2CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
311 #define PWR_WIO2SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
317 #define PWR_WIO3CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
330 #define PWR_WIO3SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
336 #define PWR_WIO4CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
349 #define PWR_WIO4SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
355 #define PWR_WIO5CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
368 #define PWR_WIO5SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
374 #define PWR_WIO6CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
387 #define PWR_WIO6SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
392 #define PWR_CPU1D1SR_CSTATE_MASK		GENMASK_32(3, 2)
394 #define PWR_CPU1D1SR_DSTATE_MASK		GENMASK_32(10, 8)
400 #define PWR_CPU2D2SR_CSTATE_MASK		GENMASK_32(3, 2)
402 #define PWR_CPU2D2SR_DSTATE_MASK		GENMASK_32(10, 8)
410 #define PWR_VERR_MINREV_MASK			GENMASK_32(3, 0)
412 #define PWR_VERR_MAJREV_MASK			GENMASK_32(7, 4)