| /optee_os/core/arch/arm/plat-mediatek/ |
| H A D | platform_config.h | 26 #define UART0_BASE 0x11002000 macro
31 #define CONSOLE_UART_BASE UART0_BASE
44 #define UART0_BASE 0x11002000 macro
48 #define CONSOLE_UART_BASE UART0_BASE
58 #define UART0_BASE 0x11005000 macro
62 #define CONSOLE_UART_BASE UART0_BASE
72 #define UART0_BASE 0x11002000 macro
76 #define CONSOLE_UART_BASE UART0_BASE
86 #define UART0_BASE 0x11001100 macro
90 #define CONSOLE_UART_BASE UART0_BASE
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| /optee_os/core/arch/arm/plat-ls/ |
| H A D | platform_config.h | 38 #define CONSOLE_UART_BASE UART0_BASE
43 #define UART0_BASE 0x021C0500 macro
52 #define UART0_BASE 0x021C0500 macro
66 #define UART0_BASE 0x021C0500 macro
76 #define UART0_BASE 0x021C0500 macro
86 #define UART0_BASE 0x021C0600 macro
96 #define UART0_BASE 0x021C0500 macro
106 #define UART0_BASE 0x021C0000 macro
116 #define UART0_BASE 0x021C0000 macro
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| /optee_os/core/arch/arm/plat-vexpress/ |
| H A D | platform_config.h | 18 #define UART0_BASE 0x1c090000 macro
34 #define UART0_BASE 0x1c090000 macro
58 #define UART0_BASE 0x09000000 macro
71 #define UART0_BASE 0x09000000 macro
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| /optee_os/core/arch/arm/plat-synquacer/ |
| H A D | platform_config.h | 17 #define UART0_BASE 0x2A400000 macro
18 #define CONSOLE_UART_BASE UART0_BASE
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| /optee_os/core/arch/arm/plat-nuvoton/ |
| H A D | platform_config.h | 17 #define UART0_BASE 0xf0000000 macro
19 #define CONSOLE_UART_BASE UART0_BASE
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| /optee_os/core/arch/arm/plat-totalcompute/ |
| H A D | platform_config.h | 23 #define UART0_BASE 0x2A410000 macro
26 #define CONSOLE_UART_BASE UART0_BASE
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| /optee_os/core/arch/arm/plat-versal/ |
| H A D | platform_config.h | 21 #define UART0_BASE 0xFF000000 macro
29 #define CONSOLE_UART_BASE UART0_BASE
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| /optee_os/core/arch/arm/plat-versal2/ |
| H A D | platform_config.h | 26 #define UART0_BASE U(0xF1920000) macro
38 #define CONSOLE_UART_BASE UART0_BASE
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| /optee_os/core/arch/riscv/plat-virt/ |
| H A D | platform_config.h | 52 #ifndef UART0_BASE
53 #define UART0_BASE 0x10000000 macro
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| H A D | main.c | 17 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART0_BASE, CORE_MMU_PGDIR_SIZE);
72 ns16550_init(&console_data, UART0_BASE, IO_WIDTH_U8, 0); in plat_console_init()
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| /optee_os/core/arch/arm/plat-ti/ |
| H A D | platform_config.h | 62 #define UART0_BASE 0x44E09000 macro
69 #define CONSOLE_UART_BASE UART0_BASE
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| /optee_os/core/arch/arm/plat-k3/ |
| H A D | platform_config.h | 12 #define UART0_BASE 0x02800000 macro
14 #define CONSOLE_UART_BASE (UART0_BASE + CFG_CONSOLE_UART * 0x10000)
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| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | platform_config.h | 55 #define UART0_BASE (MMIO_BASE + 0x07180000) macro
97 #define UART0_BASE 0xfd890000 macro
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| /optee_os/core/arch/arm/plat-imx/registers/ |
| H A D | imx8q.h | 11 #define UART0_BASE 0x5a060000 macro
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| /optee_os/core/arch/arm/plat-corstone1000/ |
| H A D | platform_config.h | 16 #define UART0_BASE 0x1a510000 macro
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| /optee_os/core/arch/arm/plat-sprd/ |
| H A D | platform_config.h | 44 #define UART0_BASE 0x70000000 macro
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| /optee_os/core/arch/arm/plat-zynqmp/ |
| H A D | platform_config.h | 64 #define UART0_BASE 0xFF000000 macro
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| H A D | conf.mk | 26 CFG_UART_BASE ?= UART0_BASE
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| /optee_os/core/arch/arm/plat-automotive_rd/ |
| H A D | platform_config.h | 52 #define UART0_BASE UL(0x2A400000) macro
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| /optee_os/core/arch/arm/plat-zynq7k/ |
| H A D | platform_config.h | 64 #define UART0_BASE 0xE0000000 macro
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| /optee_os/core/arch/arm/plat-imx/ |
| H A D | conf.mk | 477 CFG_UART_BASE ?= UART0_BASE
485 CFG_UART_BASE ?= UART0_BASE
491 CFG_UART_BASE ?= UART0_BASE
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