xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 2d65d514af870d867bb0ccb28026982e6c05272c) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate \
68	mx8mm_phyboard_polis \
69	mx8mm_phygate_tauri_l
70
71mx8mn-flavorlist = \
72	mx8mnevk
73
74mx8mp-flavorlist = \
75	mx8mpevk \
76	mx8mp_rsb3720_6g \
77	mx8mp_phyboard_pollux \
78	mx8mp_libra_fpsc
79
80mx8qm-flavorlist = \
81	mx8qmmek \
82
83mx8qx-flavorlist = \
84	mx8qxpmek \
85	mx8dxmek \
86
87mx8dxl-flavorlist = \
88	mx8dxlevk \
89
90mx8ulp-flavorlist = \
91	mx8ulpevk \
92
93mx93-flavorlist = \
94	mx93evk \
95
96mx95-flavorlist = \
97	mx95evk \
98
99mx91-flavorlist = \
100	mx91evk \
101
102ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
103$(call force,CFG_MX6,y)
104$(call force,CFG_MX6UL,y)
105$(call force,CFG_TEE_CORE_NB_CORE,1)
106$(call force,CFG_TZC380,y)
107include core/arch/arm/cpu/cortex-a7.mk
108else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
109$(call force,CFG_MX6,y)
110$(call force,CFG_MX6ULL,y)
111$(call force,CFG_TEE_CORE_NB_CORE,1)
112$(call force,CFG_TZC380,y)
113$(call force,CFG_IMX_CAAM,n)
114$(call force,CFG_NXP_CAAM,n)
115$(call force,CFG_IMX_DCP,y)
116include core/arch/arm/cpu/cortex-a7.mk
117else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
118$(call force,CFG_MX6,y)
119$(call force,CFG_MX6Q,y)
120$(call force,CFG_TEE_CORE_NB_CORE,4)
121$(call force,CFG_TZC380,y)
122else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
123$(call force,CFG_MX6,y)
124$(call force,CFG_MX6QP,y)
125$(call force,CFG_TEE_CORE_NB_CORE,4)
126else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
127$(call force,CFG_MX6,y)
128$(call force,CFG_MX6D,y)
129$(call force,CFG_TEE_CORE_NB_CORE,2)
130$(call force,CFG_TZC380,y)
131else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
132$(call force,CFG_MX6,y)
133$(call force,CFG_MX6DL,y)
134$(call force,CFG_TEE_CORE_NB_CORE,2)
135$(call force,CFG_TZC380,y)
136else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
137$(call force,CFG_MX6,y)
138$(call force,CFG_MX6S,y)
139$(call force,CFG_TEE_CORE_NB_CORE,1)
140else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
141$(call force,CFG_MX6,y)
142$(call force,CFG_MX6SL,y)
143$(call force,CFG_TEE_CORE_NB_CORE,1)
144$(call force,CFG_IMX_CAAM,n)
145$(call force,CFG_NXP_CAAM,n)
146$(call force,CFG_IMX_DCP,y)
147else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
148$(call force,CFG_MX6,y)
149$(call force,CFG_MX6SLL,y)
150$(call force,CFG_TEE_CORE_NB_CORE,1)
151$(call force,CFG_IMX_CAAM,n)
152$(call force,CFG_NXP_CAAM,n)
153$(call force,CFG_IMX_DCP,y)
154$(call force,CFG_NO_SMP,y)
155else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
156$(call force,CFG_MX6,y)
157$(call force,CFG_MX6SX,y)
158$(call force,CFG_TEE_CORE_NB_CORE,1)
159else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
160$(call force,CFG_MX7,y)
161$(call force,CFG_TEE_CORE_NB_CORE,1)
162include core/arch/arm/cpu/cortex-a7.mk
163else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
164$(call force,CFG_MX7,y)
165$(call force,CFG_TEE_CORE_NB_CORE,2)
166include core/arch/arm/cpu/cortex-a7.mk
167else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
168$(call force,CFG_MX7ULP,y)
169$(call force,CFG_TEE_CORE_NB_CORE,1)
170$(call force,CFG_TZC380,n)
171$(call force,CFG_IMX_CSU,n)
172include core/arch/arm/cpu/cortex-a7.mk
173else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
174$(call force,CFG_MX8MQ,y)
175$(call force,CFG_MX8M,y)
176$(call force,CFG_ARM64_core,y)
177$(call force,CFG_TZC380,y)
178CFG_DRAM_BASE ?= 0x40000000
179CFG_TEE_CORE_NB_CORE ?= 4
180else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
181$(call force,CFG_MX8MM,y)
182$(call force,CFG_MX8M,y)
183$(call force,CFG_ARM64_core,y)
184$(call force,CFG_TZC380,y)
185CFG_DRAM_BASE ?= 0x40000000
186CFG_TEE_CORE_NB_CORE ?= 4
187else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
188$(call force,CFG_MX8MN,y)
189$(call force,CFG_MX8M,y)
190$(call force,CFG_ARM64_core,y)
191$(call force,CFG_TZC380,y)
192CFG_DRAM_BASE ?= 0x40000000
193CFG_TEE_CORE_NB_CORE ?= 4
194else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
195$(call force,CFG_MX8MP,y)
196$(call force,CFG_MX8M,y)
197$(call force,CFG_ARM64_core,y)
198$(call force,CFG_TZC380,y)
199CFG_DRAM_BASE ?= 0x40000000
200CFG_TEE_CORE_NB_CORE ?= 4
201else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
202$(call force,CFG_MX8QM,y)
203$(call force,CFG_ARM64_core,y)
204$(call force,CFG_IMX_SNVS,n)
205CFG_IMX_LPUART ?= y
206CFG_DRAM_BASE ?= 0x80000000
207CFG_TEE_CORE_NB_CORE ?= 6
208$(call force,CFG_IMX_OCOTP,n)
209else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
210$(call force,CFG_MX8QX,y)
211$(call force,CFG_ARM64_core,y)
212$(call force,CFG_IMX_SNVS,n)
213CFG_IMX_LPUART ?= y
214CFG_DRAM_BASE ?= 0x80000000
215CFG_TEE_CORE_NB_CORE ?= 4
216$(call force,CFG_IMX_OCOTP,n)
217else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
218$(call force,CFG_MX8DXL,y)
219$(call force,CFG_ARM64_core,y)
220$(call force,CFG_IMX_SNVS,n)
221CFG_IMX_LPUART ?= y
222CFG_DRAM_BASE ?= 0x80000000
223$(call force,CFG_TEE_CORE_NB_CORE,2)
224$(call force,CFG_IMX_OCOTP,n)
225else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
226$(call force,CFG_MX8ULP,y)
227$(call force,CFG_ARM64_core,y)
228CFG_IMX_LPUART ?= y
229CFG_DRAM_BASE ?= 0x80000000
230CFG_TEE_CORE_NB_CORE ?= 2
231$(call force,CFG_NXP_SNVS,n)
232$(call force,CFG_IMX_OCOTP,n)
233CFG_IMX_MU ?= y
234CFG_IMX_ELE ?= n
235else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
236$(call force,CFG_MX93,y)
237$(call force,CFG_ARM64_core,y)
238CFG_IMX_LPUART ?= y
239CFG_DRAM_BASE ?= 0x80000000
240CFG_TEE_CORE_NB_CORE ?= 2
241$(call force,CFG_NXP_SNVS,n)
242$(call force,CFG_IMX_OCOTP,n)
243$(call force,CFG_TZC380,n)
244$(call force,CFG_CRYPTO_DRIVER,n)
245$(call force,CFG_NXP_CAAM,n)
246CFG_IMX_MU ?= y
247CFG_IMX_ELE ?= y
248else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx95-flavorlist)))
249$(call force,CFG_MX95,y)
250$(call force,CFG_ARM64_core,y)
251CFG_IMX_LPUART ?= y
252CFG_DRAM_BASE ?= 0x80000000
253CFG_TEE_CORE_NB_CORE ?= 6
254$(call force,CFG_NXP_SNVS,n)
255$(call force,CFG_IMX_OCOTP,n)
256$(call force,CFG_TZC380,n)
257$(call force,CFG_NXP_CAAM,n)
258CFG_IMX_MU ?= y
259CFG_IMX_ELE ?= y
260else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx91-flavorlist)))
261$(call force,CFG_MX91,y)
262$(call force,CFG_ARM64_core,y)
263CFG_IMX_LPUART ?= y
264CFG_DRAM_BASE ?= 0x80000000
265CFG_TEE_CORE_NB_CORE ?= 1
266$(call force,CFG_NXP_SNVS,n)
267$(call force,CFG_IMX_OCOTP,n)
268$(call force,CFG_TZC380,n)
269$(call force,CFG_NXP_CAAM,n)
270CFG_IMX_MU ?= y
271CFG_IMX_ELE ?= y
272else
273$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
274endif
275
276ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
277CFG_DDR_SIZE ?= 0x40000000
278CFG_NS_ENTRY_ADDR ?= 0x80800000
279CFG_IMX_WDOG_EXT_RESET ?= y
280endif
281
282ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
283CFG_DDR_SIZE ?= 0x40000000
284CFG_UART_BASE ?= UART1_BASE
285CFG_IMX_WDOG_EXT_RESET ?= y
286endif
287
288ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
289CFG_DDR_SIZE ?= 0x20000000
290CFG_NS_ENTRY_ADDR ?= 0x87800000
291CFG_DT_ADDR ?= 0x83100000
292CFG_UART_BASE ?= UART5_BASE
293CFG_BOOT_SECONDARY_REQUEST ?= n
294CFG_EXTERNAL_DTB_OVERLAY ?= y
295CFG_IMX_WDOG_EXT_RESET ?= y
296endif
297
298ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
299CFG_DDR_SIZE ?= 0x20000000
300CFG_NS_ENTRY_ADDR ?= 0x80800000
301CFG_BOOT_SECONDARY_REQUEST ?= n
302endif
303
304ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
305CFG_DDR_SIZE ?= 0x20000000
306CFG_NS_ENTRY_ADDR ?= 0x87800000
307CFG_DT_ADDR ?= 0x83100000
308CFG_BOOT_SECONDARY_REQUEST ?= n
309CFG_EXTERNAL_DTB_OVERLAY = y
310CFG_IMX_WDOG_EXT_RESET = y
311endif
312
313ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
314CFG_DDR_SIZE ?= 0x40000000
315CFG_NS_ENTRY_ADDR ?= 0x60800000
316CFG_UART_BASE ?= UART4_BASE
317endif
318
319ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
320	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
321	mx6dapalis mx6qapalis))
322CFG_DDR_SIZE ?= 0x40000000
323CFG_NS_ENTRY_ADDR ?= 0x12000000
324endif
325
326ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
327	mx6dlsabreauto mx6solosabreauto))
328CFG_DDR_SIZE ?= 0x80000000
329CFG_NS_ENTRY_ADDR ?= 0x12000000
330CFG_UART_BASE ?= UART4_BASE
331endif
332
333ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
334CFG_DDR_SIZE ?= 0x80000000
335CFG_UART_BASE ?= UART1_BASE
336endif
337
338ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
339CFG_DDR_SIZE ?= 0x40000000
340CFG_NS_ENTRY_ADDR ?= 0x12000000
341endif
342
343ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
344CFG_DDR_SIZE ?= 0x40000000
345CFG_NS_ENTRY_ADDR ?= 0x12000000
346CFG_UART_BASE ?= UART2_BASE
347endif
348
349ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
350CFG_NS_ENTRY_ADDR ?= 0x80800000
351CFG_DDR_SIZE ?= 0x40000000
352endif
353
354ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
355CFG_NS_ENTRY_ADDR ?= 0x80800000
356CFG_DDR_SIZE ?= 0x80000000
357endif
358
359ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
360CFG_DDR_SIZE ?= 0x80000000
361CFG_NS_ENTRY_ADDR ?= 0x80800000
362endif
363
364ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
365CFG_DDR_SIZE ?= 0x40000000
366CFG_NS_ENTRY_ADDR ?= 0x80800000
367endif
368
369ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
370CFG_DDR_SIZE ?= 0x40000000
371CFG_UART_BASE ?= UART1_BASE
372endif
373
374ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
375CFG_DDR_SIZE ?= 0x20000000
376CFG_NS_ENTRY_ADDR ?= 0x80800000
377endif
378
379ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
380CFG_DDR_SIZE ?= 0x10000000
381CFG_NS_ENTRY_ADDR ?= 0x80800000
382CFG_UART_BASE ?= UART5_BASE
383endif
384
385ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
386CFG_DDR_SIZE ?= 0x10000000
387CFG_NS_ENTRY_ADDR ?= 0x80800000
388endif
389
390ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
391CFG_DDR_SIZE ?= 0x10000000
392CFG_UART_BASE ?= UART7_BASE
393endif
394
395ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
396CFG_DDR_SIZE ?= 0xc0000000
397CFG_UART_BASE ?= UART1_BASE
398endif
399
400ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
401CFG_DDR_SIZE ?= 0x80000000
402CFG_UART_BASE ?= UART2_BASE
403endif
404
405ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
406CFG_DDR_SIZE ?= 0x40000000
407CFG_UART_BASE ?= UART3_BASE
408CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
409CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
410endif
411
412ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phyboard_polis))
413CFG_DDR_SIZE ?= 0x40000000
414CFG_UART_BASE ?= UART3_BASE
415$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
416$(call force,CFG_CORE_ARM64_PA_BITS,36)
417endif
418
419ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phygate_tauri_l))
420CFG_DDR_SIZE ?= 0x80000000
421CFG_UART_BASE ?= UART3_BASE
422$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
423$(call force,CFG_CORE_ARM64_PA_BITS,36)
424endif
425
426ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
427CFG_DDR_SIZE ?= 0x80000000
428CFG_UART_BASE ?= UART2_BASE
429endif
430
431ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
432CFG_DDR_SIZE ?= UL(0x180000000)
433CFG_UART_BASE ?= UART2_BASE
434$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
435$(call force,CFG_CORE_ARM64_PA_BITS,36)
436endif
437
438ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_libra_fpsc))
439CFG_DDR_SIZE ?= 0x40000000
440CFG_UART_BASE ?= UART4_BASE
441$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
442$(call force,CFG_CORE_ARM64_PA_BITS,36)
443endif
444
445ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_phyboard_pollux))
446CFG_DDR_SIZE ?= 0x40000000
447CFG_UART_BASE ?= UART1_BASE
448$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
449$(call force,CFG_CORE_ARM64_PA_BITS,36)
450endif
451
452ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
453CFG_DDR_SIZE ?= UL(0x180000000)
454CFG_UART_BASE ?= UART3_BASE
455CFG_TZDRAM_START ?= 0x56000000
456$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
457$(call force,CFG_CORE_ARM64_PA_BITS,36)
458endif
459
460ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
461CFG_DDR_SIZE ?= 0x80000000
462CFG_UART_BASE ?= UART0_BASE
463CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
464CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
465CFG_CORE_ARM64_PA_BITS ?= 40
466endif
467
468ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
469CFG_DDR_SIZE ?= 0x40000000
470CFG_UART_BASE ?= UART0_BASE
471$(call force,CFG_MX8DX,y)
472endif
473
474ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
475CFG_DDR_SIZE ?= 0x40000000
476CFG_UART_BASE ?= UART0_BASE
477CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
478CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
479CFG_CORE_ARM64_PA_BITS ?= 40
480endif
481
482ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
483CFG_DDR_SIZE ?= 0x80000000
484CFG_UART_BASE ?= UART5_BASE
485endif
486
487ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk mx91evk))
488CFG_DDR_SIZE ?= 0x80000000
489CFG_UART_BASE ?= UART1_BASE
490endif
491
492ifneq (,$(filter $(PLATFORM_FLAVOR),mx95evk))
493CFG_DDR_SIZE ?= 0x80000000
494CFG_UART_BASE ?= UART1_BASE
495CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
496CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
497CFG_CORE_ARM64_PA_BITS ?= 40
498endif
499
500# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
501ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
502	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
503include core/arch/arm/cpu/cortex-a9.mk
504
505$(call force,CFG_PL310,y)
506
507CFG_PL310_LOCKED ?= y
508CFG_ENABLE_SCTLR_RR ?= y
509CFG_IMX_SCU ?= y
510endif
511
512ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
513CFG_DRAM_BASE ?= 0x10000000
514endif
515
516ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
517	$(CFG_MX6SX)))
518CFG_DRAM_BASE ?= 0x80000000
519endif
520
521ifeq ($(filter y, $(CFG_MX7)), y)
522CFG_INIT_CNTVOFF ?= y
523CFG_DRAM_BASE ?= 0x80000000
524endif
525
526ifeq ($(filter y, $(CFG_MX7ULP)), y)
527CFG_INIT_CNTVOFF ?= y
528CFG_DRAM_BASE ?= UL(0x60000000)
529$(call force,CFG_IMX_LPUART,y)
530$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
531endif
532
533ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
534$(call force,CFG_GIC,y)
535
536CFG_BOOT_SECONDARY_REQUEST ?= y
537CFG_DT ?= y
538CFG_DTB_MAX_SIZE ?= 0x20000
539CFG_PAGEABLE_ADDR ?= 0
540CFG_PSCI_ARM32 ?= y
541CFG_SECURE_TIME_SOURCE_REE ?= y
542CFG_UART_BASE ?= UART1_BASE
543endif
544
545ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
546$(call force,CFG_IMX_UART,y)
547CFG_IMX_SNVS ?= y
548endif
549
550ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
551CFG_IMX_CSU ?= y
552endif
553
554ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
555CFG_HWSUPP_MEM_PERM_WXN = n
556CFG_IMX_WDOG ?= y
557endif
558
559ifeq ($(CFG_ARM64_core),y)
560# arm-v8 platforms
561include core/arch/arm/cpu/cortex-armv8-0.mk
562$(call force,CFG_ARM_GICV3,y)
563$(call force,CFG_GIC,y)
564$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
565$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
566
567CFG_CRYPTO_WITH_CE ?= y
568
569supported-ta-targets = ta_arm64
570endif
571
572CFG_TZDRAM_SIZE ?= 0x01e00000
573CFG_SHMEM_SIZE ?= 0x00200000
574CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
575CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
576
577# Enable embedded tests by default
578CFG_ENABLE_EMBEDDED_TESTS ?= y
579CFG_ATTESTATION_PTA ?= y
580
581# Set default heap size for imx platforms to 128k
582CFG_CORE_HEAP_SIZE ?= 131072
583
584CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
585CFG_MMAP_REGIONS ?= 24
586
587# SE05X and OCOTP both implement tee_otp_get_die_id()
588ifeq ($(CFG_NXP_SE05X),y)
589$(call force,CFG_IMX_OCOTP,n)
590$(call force,CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID,n)
591endif
592CFG_IMX_OCOTP ?= y
593CFG_IMX_DIGPROG ?= y
594CFG_PKCS11_TA ?= y
595CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID ?= y
596
597# Almost all platforms include CAAM HW Modules, except the
598# ones forced to be disabled
599CFG_NXP_CAAM ?= n
600
601ifeq ($(CFG_NXP_CAAM),y)
602ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
603CFG_IMX_SC ?= y
604CFG_IMX_MU ?= y
605endif
606
607else
608
609ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
610CFG_IMX_CAAM ?= y
611endif
612
613endif
614