| #
e27b0796 |
| 25-Jan-2025 |
Yu-Chien Peter Lin <peter.lin@sifive.com> |
riscv: plat-virt: move stack alignment definition
The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configurat
riscv: plat-virt: move stack alignment definition
The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configuration to riscv.h.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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|
| #
43730326 |
| 28-Feb-2025 |
Huang Borong <huangborong@bosc.ac.cn> |
riscv: plat-virt: add APLIC and IMSIC support for QEMU virt platform
- Add APLIC and IMSIC configurations for the QEMU virt platform.
- Override the interrupt controller initialization and interrupt
riscv: plat-virt: add APLIC and IMSIC support for QEMU virt platform
- Add APLIC and IMSIC configurations for the QEMU virt platform.
- Override the interrupt controller initialization and interrupt handler
functions when using APLIC or IMSIC.
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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|
| #
7b76de3d |
| 24-Jul-2024 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Let platform choose native and foreign interrupts
Platform may want to choose different types of native and foreign
interrupts. This commit adds two definitions for the platforms:
1. PL
core: riscv: Let platform choose native and foreign interrupts
Platform may want to choose different types of native and foreign
interrupts. This commit adds two definitions for the platforms:
1. PLAT_THREAD_EXCP_FOREIGN_INTR: to define platform specific foreign
interrupts
2. PLAT_THREAD_EXCP_NATIVE_INTR: to define platform specific native
interrupts.
For RISC-V virt machine, we define all external/mtimer/software
interrupts as foreign interrupts. For RISC-V spike platform, we define
external interrupts as foreign interrupts, and mtimer/software
interrupts as native interrupts.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| #
9478318b |
| 26-Sep-2023 |
Alvin Chang <alvinga@andestech.com> |
riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1
Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x6
riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1
Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x600000,
and the number of interrupt sources should be 95.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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|
| #
e2f6d2fb |
| 30-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: add plat-virt
Add Qemu Virt RISC-V platform.
Reference:
https://www.qemu.org/docs/master/system/riscv/virt.html
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: J
core: riscv: add plat-virt
Add Qemu Virt RISC-V platform.
Reference:
https://www.qemu.org/docs/master/system/riscv/virt.html
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|