| #
7bf5e91c |
| 30-Aug-2022 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: plat-ls: remove OP-TEE support for LS1021A-QDS platform
LS1021A-QDS does not support OP-TEE anymore, removing its
support.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jer
core: plat-ls: remove OP-TEE support for LS1021A-QDS platform
LS1021A-QDS does not support OP-TEE anymore, removing its
support.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| #
a7bd58f7 |
| 30-Aug-2022 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: plat-ls: remove OP-TEE support for LS1021A-TWR platform
LS1021A-TWR does not support OP-TEE anymore, removing its
support.
Since LS1021A-TWR was default platform for LS, updating default
platf
core: plat-ls: remove OP-TEE support for LS1021A-TWR platform
LS1021A-TWR does not support OP-TEE anymore, removing its
support.
Since LS1021A-TWR was default platform for LS, updating default
platform also to LS1012A-RDB
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| #
495c0cbd |
| 08-Jul-2022 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: plat-ls: remove OP-TEE support for LS1012A-FRWY platform
LS1012A-FRWY does not support OP-TEE anymore, removing its
support.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: J
core: plat-ls: remove OP-TEE support for LS1012A-FRWY platform
LS1012A-FRWY does not support OP-TEE anymore, removing its
support.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| #
0117a8ef |
| 30-May-2022 |
Clement Faure <clement.faure@nxp.com> |
core: ls: add CAAM_SIZE values for LS platforms
Add CAAM_SIZE values for all LS platforms.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| #
45800c40 |
| 23-Dec-2020 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: ls: fix GIC offset for ls1043a rev1 and rev1.1
GIC offsets are different on ls1043a depending of the SoC revision
1 or 1.1
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by
core: ls: fix GIC offset for ls1043a rev1 and rev1.1
GIC offsets are different on ls1043a depending of the SoC revision
1 or 1.1
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| #
1a0e267a |
| 19-Jan-2022 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: plat-ls: ls1028a: fix uart address
Fix UART0_BASE address for LS1028 platform
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
|
| #
824d3085 |
| 15-Dec-2020 |
Franck LENORMAND <franck.lenormand@nxp.com> |
core: plat-ls: ls1012a: Fix GIC offset
The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Si
core: plat-ls: ls1012a: Fix GIC offset
The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| #
0596632d |
| 22-Mar-2021 |
Clement Faure <clement.faure@nxp.com> |
core: ls: add CAAM_BASE for all LS platforms
Add CAAM_BASE for the following LS platforms:
- ls1021aqds/atwr
- ls1088ardb
- ls2088ardb
- ls1028ardb
- lx2160aqds
Signed-off-by: Clement Faure <c
core: ls: add CAAM_BASE for all LS platforms
Add CAAM_BASE for the following LS platforms:
- ls1021aqds/atwr
- ls1088ardb
- ls2088ardb
- ls1028ardb
- lx2160aqds
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| #
1a121401 |
| 03-Jun-2020 |
Manish Tomar <manish.tomar@nxp.com> |
core: ls: add LX2160A-QDS platform
Add support for Layerscape® LX2160A-QDS from NXP.
Dynamic shared memory is also enabled.
Signed-off-by: Manish Tomar <manish.tomar@nxp.com>
Signed-off-by: Sahil M
core: ls: add LX2160A-QDS platform
Add support for Layerscape® LX2160A-QDS from NXP.
Dynamic shared memory is also enabled.
Signed-off-by: Manish Tomar <manish.tomar@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| #
e989a6c4 |
| 01-Feb-2021 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
console: lx2160A: fix uart clock and baud rate
Currently there are garbled messages from OP-TEE due to
assumption that platform clock is always 700MHz. This is
not correct as LX2 supports variable p
console: lx2160A: fix uart clock and baud rate
Currently there are garbled messages from OP-TEE due to
assumption that platform clock is always 700MHz. This is
not correct as LX2 supports variable platform frequency.
It could be one of the 600, 650, 700, 750 Mhz based on
the RCW configuration.
Ideally OPTEE should read RCW registers from Global Utilities
Register block and derive the uart clock based on platform pll
frequency. But there is no need for this as Baud Rate is already
configured in PL011 by the previous boot stages in TF-A.
This fix calls pl011_init() with zero for baud rate => It won't be
reinitalized in OP-TEE.
Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| #
e555de5f |
| 03-Apr-2020 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
core: plat-ls: Enable CAAM driver for PLATFORM lx2160ardb
Enable and test CAAM driver on lx2160ardb platform for
hash, ciphers and RSA
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-
core: plat-ls: Enable CAAM driver for PLATFORM lx2160ardb
Enable and test CAAM driver on lx2160ardb platform for
hash, ciphers and RSA
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| #
fc733424 |
| 17-Feb-2020 |
Priyanka Singh <priyanka.singh@nxp.com> |
core: plat-ls: Fix gic offsets for platform LS1046ARDB
Fix GIC offsets for platform LS1046ARDB
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@n
core: plat-ls: Fix gic offsets for platform LS1046ARDB
Fix GIC offsets for platform LS1046ARDB
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| #
f6c354e2 |
| 12-Feb-2020 |
Priyanka Singh <priyanka.singh@nxp.com> |
core: plat-ls: Enable caam support for platform LS1046ARDB
Enable CAAM support for platform LS1046ARDB
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.ma
core: plat-ls: Enable caam support for platform LS1046ARDB
Enable CAAM support for platform LS1046ARDB
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| #
5006adae |
| 01-Aug-2019 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
plat-ls: add LS1028ARDB platform
Adds support for the The Layerscape® LS1028A reference
design board (LS1028ARDB) from NXP.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Joaki
plat-ls: add LS1028ARDB platform
Adds support for the The Layerscape® LS1028A reference
design board (LS1028ARDB) from NXP.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
show more ...
|
| #
73094386 |
| 10-Dec-2018 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
plat-ls: NXP LX2160ARDB platform support is added
Added support for armv8 platform flavour.
- PLATFORM = ls-lx2160ardb
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Jerome Foris
plat-ls: NXP LX2160ARDB platform support is added
Added support for armv8 platform flavour.
- PLATFORM = ls-lx2160ardb
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| #
a06857f9 |
| 10-Aug-2018 |
Vinitha V Pillai <vinitha.pillai@nxp.com> |
plat-ls:add LS2088ARDB platform flavors
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
|
| #
0ecda02b |
| 10-Aug-2018 |
Vinitha V Pillai <vinitha.pillai@nxp.com> |
plat-ls:add LS1088ARDB platform flavors
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.co
plat-ls:add LS1088ARDB platform flavors
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
show more ...
|
| #
17eba58a |
| 10-Aug-2018 |
Vinitha V Pillai <vinitha.pillai@nxp.com> |
plat-ls:add LS1012AFRWY platform flavors
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.c
plat-ls:add LS1012AFRWY platform flavors
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
show more ...
|
| #
929b5671 |
| 06-Aug-2018 |
Vinitha V Pillai <vinitha.pillai.nxp.com> |
core:arch:arm:plat-ls: make generic layout for all platforms
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <
core:arch:arm:plat-ls: make generic layout for all platforms
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
show more ...
|
| #
700b428d |
| 17-May-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-ls: move to generic RAM layout
Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using header generic_ram_layout.h.
ls1021atwr:
- Secure RAM [bc00.000
plat-ls: move to generic RAM layout
Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using header generic_ram_layout.h.
ls1021atwr:
- Secure RAM [bc00.0000 bfe0.0000[ configurable.
- Static SHM [bfe0.0000 bff0.0000[ configurable.
ls1021aqds:
- Secure RAM [fc00.0000 ffe0.0000[ configurable.
- Static SHM [ffe0.0000 ffff.ffff] configurable.
ls1012ardb:
- Secure RAM [bc00.0000 bfe0.0000[ configurable.
- Static SHM [bfe0.0000 c000.0000[ configurable.
ls1043ardb:
- Secure RAM [fc00.0000 ffe0.0000[ configurable.
- Static SHM [bfe0.0000 c000.0000[ configurable.
ls1046ardb:
- Secure RAM [fc00.0000 ffe0.0000[ configurable.
- Static SHM [bfe0.0000 c000.0000[ configurable.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
show more ...
|
| #
3235302e |
| 26-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-ls: move some CFG_'s from platform_config.h to conf.mk
Remove CFG_DDR_TEETZ_RESERVED_START/_SIZE: internal to platform.
Remove CFG_PUB_RAM_SIZE, use TEE_SHMEM_SIZE instead.
Remove useless defin
plat-ls: move some CFG_'s from platform_config.h to conf.mk
Remove CFG_DDR_TEETZ_RESERVED_START/_SIZE: internal to platform.
Remove CFG_PUB_RAM_SIZE, use TEE_SHMEM_SIZE instead.
Remove useless definition of DDR_PHYS_START, DDR_SIZE, DRAM0_BASE/_SIZE,
CFG_DDR_START/_SIZE.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
show more ...
|
| #
f6bbec8e |
| 24-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR
TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to ov
core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR
TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| #
6f4e40ab |
| 25-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE
Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configura
core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE
Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.
This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they
do not mess with the platform configuration directives. Yet, the old
CFG_SHMEM_START/SIZE directives can still be used by platform_config.h
to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| #
247bea90 |
| 25-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE
Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be config
core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE
Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.
This change renames these macros so that they do not mess with the
platform configuration directives.
Old macro label New macro label
CFG_TA_RAM_START TA_RAM_START
CFG_TA_RAM_SIZE TA_RAM_SIZE
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| #
446cc62a |
| 25-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE
Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be c
core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE
Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.
This change renames these macros so that they do not mess with the
platform configuration directives.
Old macro label New macro label
CFG_TEE_RAM_START TEE_RAM_START
CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE
CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|