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/optee_os/core/include/drivers/
H A Dtzc380.h40 #define TZC400_REG_SIZE U(0x1000)
42 #define BUILD_CONFIG_OFF U(0x000)
43 #define ACTION_OFF U(0x004)
44 #define LOCKDOWN_RANGE_OFF U(0x008)
45 #define LOCKDOWN_SELECT_OFF U(0x00C)
46 #define INT_STATUS U(0x010)
47 #define INT_CLEAR U(0x014)
49 #define FAIL_ADDRESS_LOW_OFF U(0x020)
50 #define FAIL_ADDRESS_HIGH_OFF U(0x024)
51 #define FAIL_CONTROL_OFF U(0x028)
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H A Dstm32mp21_rcc.h11 #define RCC_SECCFGR0 U(0x0)
12 #define RCC_SECCFGR1 U(0x4)
13 #define RCC_SECCFGR2 U(0x8)
14 #define RCC_SECCFGR3 U(0xC)
15 #define RCC_PRIVCFGR0 U(0x10)
16 #define RCC_PRIVCFGR1 U(0x14)
17 #define RCC_PRIVCFGR2 U(0x18)
18 #define RCC_PRIVCFGR3 U(0x1C)
19 #define RCC_RCFGLOCKR0 U(0x20)
20 #define RCC_RCFGLOCKR1 U(0x24)
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H A Dstm32mp25_rcc.h11 #define RCC_SECCFGR0 U(0x0)
12 #define RCC_SECCFGR1 U(0x4)
13 #define RCC_SECCFGR2 U(0x8)
14 #define RCC_SECCFGR3 U(0xC)
15 #define RCC_PRIVCFGR0 U(0x10)
16 #define RCC_PRIVCFGR1 U(0x14)
17 #define RCC_PRIVCFGR2 U(0x18)
18 #define RCC_PRIVCFGR3 U(0x1C)
19 #define RCC_RCFGLOCKR0 U(0x20)
20 #define RCC_RCFGLOCKR1 U(0x24)
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H A Dtzc400.h67 #define TZC400_REG_SIZE U(0x1000)
69 #define BUILD_CONFIG_OFF U(0x000)
70 #define ACTION_OFF U(0x004)
71 #define GATE_KEEPER_OFF U(0x008)
72 #define SPECULATION_CTRL_OFF U(0x00c)
73 #define INT_STATUS U(0x010)
74 #define INT_CLEAR U(0x014)
76 #define FAIL_ADDRESS_LOW_OFF U(0x020)
77 #define FAIL_ADDRESS_HIGH_OFF U(0x024)
78 #define FAIL_CONTROL_OFF U(0x028)
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H A Dls_i2c.h23 #define I2C_IBCR_MDIS U(0x80)
26 #define I2C_IBCR_IBIE U(0x40)
37 #define I2C_IBCR_MSSL U(0x20)
40 #define I2C_IBCR_TXRX U(0x10)
51 #define I2C_IBCR_NOACK U(0x08)
60 #define I2C_IBCR_RSTA U(0x04)
63 #define I2C_IBCR_DMAEN U(0x02)
66 #define I2C_IBSR_TCF U(0x80)
69 #define I2C_IBSR_IBB U(0x20)
72 #define I2C_IBSR_IBAL U(0x10)
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H A Dstm32mp13_rcc.h11 #define RCC_SECCFGR U(0x0)
12 #define RCC_MP_SREQSETR U(0x100)
13 #define RCC_MP_SREQCLRR U(0x104)
14 #define RCC_MP_APRSTCR U(0x108)
15 #define RCC_MP_APRSTSR U(0x10C)
16 #define RCC_PWRLPDLYCR U(0x110)
17 #define RCC_MP_GRSTCSETR U(0x114)
18 #define RCC_BR_RSTSCLRR U(0x118)
19 #define RCC_MP_RSTSSETR U(0x11C)
20 #define RCC_MP_RSTSCLRR U(0x120)
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H A Dls_gpio.h18 #define MAX_GPIO_PINS U(31)
24 #define GPIODIR U(0x0) /* direction register */
25 #define GPIOODR U(0x4) /* open drain register */
26 #define GPIODAT U(0x8) /* data register */
27 #define GPIOIER U(0xc) /* interrupt event register */
28 #define GPIOIMR U(0x10) /* interrupt mask register */
29 #define GPIOICR U(0x14) /* interrupt control register */
30 #define GPIOIBE U(0x18) /* input buffer enable register */
/optee_os/core/arch/arm/include/kernel/
H A Dtz_ssvce_def.h15 #define CPSR_OFFSET U(0x00)
16 #define STACK_INT_USAGE U(0x04)
22 #define SSAPI_RET_FROM_INT_SERV U(4)
23 #define SSAPI_RET_FROM_RPC_SERV U(5)
29 #define SEC_INVALID_ENTRY U(0)
30 #define SEC_PRE_INIT_ENTRY U(1)
31 #define SEC_RET_FROM_INT_ENTRY U(2)
32 #define SEC_RET_FROM_RPC_ENTRY U(3)
33 #define SEC_NORMAL_ENTRY U(4)
39 #define SEC_EXIT_NORMAL U(1)
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H A Dtz_proc_def.h18 #define CP15_CONFIG_CPU_ID_MASK U(0x00000003)
19 #define CPU_ID0 U(0x00000000)
20 #define CPU_ID1 U(0x00000001)
25 #define CP15_CONFIG_NS_MASK U(0x00000001)
26 #define CP15_CONFIG_IRQ_MASK U(0x00000002)
27 #define CP15_CONFIG_FIQ_MASK U(0x00000004)
28 #define CP15_CONFIG_EA_MASK U(0x00000008)
29 #define CP15_CONFIG_FW_MASK U(0x00000010)
30 #define CP15_CONFIG_AW_MASK U(0x00000020)
31 #define CP15_CONFIG_nET_MASK U(0x00000040)
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/optee_os/core/include/
H A Doptee_rpc_cmd.h28 #define OPTEE_RPC_CMD_LOAD_TA U(0)
36 #define OPTEE_RPC_CMD_RPMB U(1)
41 #define OPTEE_RPC_CMD_FS U(2)
52 #define OPTEE_RPC_CMD_GET_TIME U(3)
75 #define OPTEE_RPC_CMD_NOTIFICATION U(4)
76 #define OPTEE_RPC_NOTIFICATION_WAIT U(0)
77 #define OPTEE_RPC_NOTIFICATION_SEND U(1)
84 #define OPTEE_RPC_CMD_SUSPEND U(5)
95 #define OPTEE_RPC_CMD_SHM_ALLOC U(6)
97 #define OPTEE_RPC_SHM_TYPE_APPL U(0)
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H A Doptee_msg.h25 #define OPTEE_MSG_ATTR_TYPE_NONE U(0x0)
26 #define OPTEE_MSG_ATTR_TYPE_VALUE_INPUT U(0x1)
27 #define OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT U(0x2)
28 #define OPTEE_MSG_ATTR_TYPE_VALUE_INOUT U(0x3)
29 #define OPTEE_MSG_ATTR_TYPE_RMEM_INPUT U(0x5)
30 #define OPTEE_MSG_ATTR_TYPE_RMEM_OUTPUT U(0x6)
31 #define OPTEE_MSG_ATTR_TYPE_RMEM_INOUT U(0x7)
35 #define OPTEE_MSG_ATTR_TYPE_TMEM_INPUT U(0x9)
36 #define OPTEE_MSG_ATTR_TYPE_TMEM_OUTPUT U(0xa)
37 #define OPTEE_MSG_ATTR_TYPE_TMEM_INOUT U(0xb)
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/optee_os/core/arch/arm/include/
H A Darm.h14 #define MIDR_PRIMARY_PART_NUM_SHIFT U(4)
15 #define MIDR_PRIMARY_PART_NUM_WIDTH U(12)
18 #define MIDR_IMPLEMENTER_SHIFT U(24)
19 #define MIDR_IMPLEMENTER_WIDTH U(8)
21 #define MIDR_IMPLEMENTER_ARM U(0x41)
23 #define MIDR_VARIANT_SHIFT U(20)
24 #define MIDR_VARIANT_WIDTH U(4)
27 #define MIDR_REVISION_SHIFT U(0)
28 #define MIDR_REVISION_WIDTH U(4)
31 #define CORTEX_A5_PART_NUM U(0xC05)
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H A Darm64.h44 #define TTBR_ASID_MASK U(0xff)
45 #define TTBR_ASID_SHIFT U(48)
47 #define CLIDR_LOUIS_SHIFT U(21)
48 #define CLIDR_LOC_SHIFT U(24)
49 #define CLIDR_FIELD_WIDTH U(3)
51 #define CSSELR_LEVEL_SHIFT U(1)
68 #define DAIF_F_SHIFT U(6)
75 #define SPSR_MODE_RW_SHIFT U(4)
76 #define SPSR_MODE_RW_MASK U(0x1)
77 #define SPSR_MODE_RW_64 U(0x0)
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H A Dffa.h29 #define FFA_VERSION_MAJOR_SHIFT U(16)
30 #define FFA_VERSION_MAJOR_MASK U(0x7FFF)
31 #define FFA_VERSION_MINOR_SHIFT U(0)
32 #define FFA_VERSION_MINOR_MASK U(0xFFFF)
46 #define FFA_ERROR U(0x84000060)
47 #define FFA_SUCCESS_32 U(0x84000061)
48 #define FFA_SUCCESS_64 U(0xC4000061)
49 #define FFA_INTERRUPT U(0x84000062)
50 #define FFA_VERSION U(0x84000063)
51 #define FFA_FEATURES U(0x84000064)
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H A Darm32.h88 #define CPACR_CP_ACCESS_DENIED U(0x0)
89 #define CPACR_CP_ACCESS_PL1_ONLY U(0x1)
90 #define CPACR_CP_ACCESS_FULL U(0x3)
94 #define DACR_DOMAIN_PERM_NO_ACCESS U(0x0)
95 #define DACR_DOMAIN_PERM_CLIENT U(0x1)
96 #define DACR_DOMAIN_PERM_MANAGER U(0x3)
101 #define PAR_PA_SHIFT U(12)
117 #define TTBCR_T0SZ_SHIFT U(0)
119 #define TTBCR_IRGN0_SHIFT U(8)
120 #define TTBCR_ORGN0_SHIFT U(10)
[all …]
/optee_os/core/arch/arm/plat-telechips/tcc805x/
H A Dplatform_config.h16 #define TCC_IO_BASE U(0x10000000)
17 #define TCC_IO_SIZE U(0x10000000)
20 #define GICD_BASE U(0x17301000)
21 #define GICC_BASE U(0x17302000)
24 #define CONSOLE_UART_BASE U(0x16600000)
29 #define OTP_CTRL_BASE U(0x19101000)
30 #define OTP_CMD_BASE U(0xE0004000)
33 #define TZC_BASE U(0xE8300000)
34 #define TZC_SIZE U(0x00100000)
35 #define TZC_OMC_BASE (TZC_BASE + U(0x80000))
[all …]
/optee_os/core/arch/arm/include/sm/
H A Dpsci.h12 #define PSCI_VERSION_0_2 U(0x00000002)
13 #define PSCI_VERSION_1_0 U(0x00010000)
14 #define PSCI_VERSION_1_1 U(0x00010001)
15 #define PSCI_VERSION U(0x84000000)
16 #define PSCI_CPU_SUSPEND U(0x84000001)
17 #define PSCI_CPU_OFF U(0x84000002)
18 #define PSCI_CPU_ON U(0x84000003)
19 #define PSCI_CPU_ON_SMC64 (PSCI_CPU_ON | U(0x40000000))
20 #define PSCI_AFFINITY_INFO U(0x84000004)
21 #define PSCI_MIGRATE U(0x84000005)
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H A Doptee_smc.h20 #define OPTEE_SMC_32 U(0)
21 #define OPTEE_SMC_64 U(0x40000000)
22 #define OPTEE_SMC_FAST_CALL U(0x80000000)
23 #define OPTEE_SMC_STD_CALL U(0)
25 #define OPTEE_SMC_OWNER_MASK U(0x3F)
26 #define OPTEE_SMC_OWNER_SHIFT U(24)
28 #define OPTEE_SMC_FUNC_MASK U(0xFFFF)
49 #define OPTEE_SMC_OWNER_ARCH U(0)
50 #define OPTEE_SMC_OWNER_CPU U(1)
51 #define OPTEE_SMC_OWNER_SIP U(2)
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/optee_os/core/arch/riscv/include/tee/
H A Doptee_abi.h18 #define OPTEE_ABI_32 U(0)
19 #define OPTEE_ABI_64 U(0x40000000)
20 #define OPTEE_ABI_FAST_CALL U(0x80000000)
21 #define OPTEE_ABI_STD_CALL U(0)
23 #define OPTEE_ABI_OWNER_MASK U(0x3F)
24 #define OPTEE_ABI_OWNER_SHIFT U(24)
26 #define OPTEE_ABI_FUNC_MASK U(0xFFFF)
47 #define OPTEE_ABI_OWNER_ARCH U(0)
48 #define OPTEE_ABI_OWNER_CPU U(1)
49 #define OPTEE_ABI_OWNER_SIP U(2)
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/optee_os/core/arch/arm/plat-stm32mp1/
H A Dplatform_config.h125 #define CFG0_OTP_CLOSED_DEVICE U(0x3F)
132 #define HW2_OTP_IWDG_HW_ENABLE_SHIFT U(3)
133 #define HW2_OTP_IWDG_FZ_STOP_SHIFT U(5)
134 #define HW2_OTP_IWDG_FZ_STANDBY_SHIFT U(7)
165 #define GPIO_BANK_A 0U
180 #define TAMP_BKP_REGISTER_COUNT U(32)
204 #define DBGMCU_IDC U(0x0)
207 #define DBGMCU_IDC_REV_ID_SHIFT U(16)
260 #define STM32MP135C_PART_NB U(0x05010000)
261 #define STM32MP135A_PART_NB U(0x05010001)
[all …]
/optee_os/core/arch/riscv/include/mm/
H A Dcore_mmu_arch.h32 #define RISCV_MMU_MODE U(39)
34 #define RISCV_MMU_MODE U(32)
40 #define RISCV_SATP_MODE_SHIFT U(60)
41 #define RISCV_SATP_ASID_SHIFT U(44)
42 #define RISCV_SATP_ASID_WIDTH U(16)
44 #define RISCV_MMU_PA_WIDTH U(56)
45 #define RISCV_MMU_VA_WIDTH U(57)
48 #define RISCV_SATP_MODE_SHIFT U(60)
49 #define RISCV_SATP_ASID_SHIFT U(44)
50 #define RISCV_SATP_ASID_WIDTH U(16)
[all …]
/optee_os/core/drivers/crypto/stm32/
H A Dstm32_pka.c32 #define INT8_LEN U(8)
42 #define _PKA_CR U(0x0)
43 #define _PKA_SR U(0x4)
44 #define _PKA_CLRFR U(0x8)
45 #define _PKA_VERR U(0x1FF4)
46 #define _PKA_IPIDR U(0x1FF8)
50 #define _PKA_CR_MODE_R2MODN U(0x01)
51 #define _PKA_CR_MODE_SHIFT U(0x08)
52 #define _PKA_CR_MODE_ADD U(0x09)
53 #define _PKA_CR_MODE_ECC_KP U(0x20)
[all …]
/optee_os/core/drivers/
H A Dopenedges_omc.c16 #define ACTION_OFF U(0x1004)
18 #define INT_STATUS U(0x1010)
19 #define INT_CLEAR U(0x1014)
20 #define FAIL_ADDRESS_LOW_OFF U(0x1020)
21 #define FAIL_ADDRESS_HIGH_OFF U(0x1024)
22 #define FAIL_CONTROL_OFF U(0x1028)
23 #define FAIL_ID_OFF U(0x102c)
24 #define FAIL_DIRECTION_OFF(d) (U(0x20) * (d))
26 #define REGION_COUNT U(17)
27 #define REGION_BASE_LOW_OFF U(0x1100)
[all …]
/optee_os/core/arch/arm/plat-telechips/drivers/
H A Dtcc_otp.c13 #define OTP_CTRL_SIZE U(0x1000)
14 #define OTP_CMD_SIZE U(0x1000)
16 #define GENERAL_STATUS U(0x0)
17 #define READ_STATUS U(0x4)
18 #define PROG_STATUS U(0x8)
19 #define OTP_ADDRESS U(0x10)
20 #define OTP_CONTROL U(0x14)
21 #define READ_DATA_PAYLOAD0 U(0x20)
22 #define READ_DATA_PAYLOAD1 U(0x24)
23 #define READ_DATA_PAYLOAD2 U(0x28)
[all …]
/optee_os/core/arch/arm/plat-stm32mp1/drivers/
H A Dstm32mp1_syscfg.c21 #define SYSCFG_SRAM3ERASER U(0x10)
22 #define SYSCFG_SRAM3KR U(0x14)
23 #define SYSCFG_IOCTRLSETR U(0x18)
24 #define SYSCFG_CMPCR U(0x20)
25 #define SYSCFG_CMPENSETR U(0x24)
26 #define SYSCFG_CMPSD1CR U(0x30)
27 #define SYSCFG_CMPSD2CR U(0x40)
28 #define SYSCFG_HSLVEN0R U(0x50)
29 #define SYSCFG_IDC U(0x380)
30 #define SYSCFG_IOSIZE U(0x400)
[all …]

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