Lines Matching refs:U
44 #define TTBR_ASID_MASK U(0xff)
45 #define TTBR_ASID_SHIFT U(48)
47 #define CLIDR_LOUIS_SHIFT U(21)
48 #define CLIDR_LOC_SHIFT U(24)
49 #define CLIDR_FIELD_WIDTH U(3)
51 #define CSSELR_LEVEL_SHIFT U(1)
68 #define DAIF_F_SHIFT U(6)
75 #define SPSR_MODE_RW_SHIFT U(4)
76 #define SPSR_MODE_RW_MASK U(0x1)
77 #define SPSR_MODE_RW_64 U(0x0)
78 #define SPSR_MODE_RW_32 U(0x1)
80 #define SPSR_64_MODE_SP_SHIFT U(0)
81 #define SPSR_64_MODE_SP_MASK U(0x1)
82 #define SPSR_64_MODE_SP_EL0 U(0x0)
83 #define SPSR_64_MODE_SP_ELX U(0x1)
85 #define SPSR_64_MODE_EL_SHIFT U(2)
86 #define SPSR_64_MODE_EL_MASK U(0x3)
87 #define SPSR_64_MODE_EL1 U(0x1)
88 #define SPSR_64_MODE_EL0 U(0x0)
90 #define SPSR_64_DAIF_SHIFT U(6)
91 #define SPSR_64_DAIF_MASK U(0xf)
95 #define SPSR_32_AIF_SHIFT U(6)
96 #define SPSR_32_AIF_MASK U(0x7)
98 #define SPSR_32_E_SHIFT U(9)
99 #define SPSR_32_E_MASK U(0x1)
100 #define SPSR_32_E_LITTLE U(0x0)
101 #define SPSR_32_E_BIG U(0x1)
103 #define SPSR_32_T_SHIFT U(5)
104 #define SPSR_32_T_MASK U(0x1)
105 #define SPSR_32_T_ARM U(0x0)
106 #define SPSR_32_T_THUMB U(0x1)
108 #define SPSR_32_MODE_SHIFT U(0)
109 #define SPSR_32_MODE_MASK U(0xf)
110 #define SPSR_32_MODE_USR U(0x0)
127 #define TCR_T0SZ_SHIFT U(0)
129 #define TCR_IRGN0_SHIFT U(8)
130 #define TCR_ORGN0_SHIFT U(10)
131 #define TCR_SH0_SHIFT U(12)
132 #define TCR_T1SZ_SHIFT U(16)
135 #define TCR_IRGN1_SHIFT U(24)
136 #define TCR_ORGN1_SHIFT U(26)
137 #define TCR_SH1_SHIFT U(28)
138 #define TCR_EL1_IPS_SHIFT U(32)
149 #define TCR_XRGNX_NC U(0x0)
151 #define TCR_XRGNX_WB U(0x1)
153 #define TCR_XRGNX_WT U(0x2)
155 #define TCR_XRGNX_WBWA U(0x3)
158 #define TCR_SHX_NSH U(0x0)
160 #define TCR_SHX_OSH U(0x2)
162 #define TCR_SHX_ISH U(0x3)
164 #define ESR_EC_SHIFT U(26)
165 #define ESR_EC_MASK U(0x3f)
167 #define ESR_EC_UNKNOWN U(0x00)
168 #define ESR_EC_WFI U(0x01)
169 #define ESR_EC_AARCH32_CP15_32 U(0x03)
170 #define ESR_EC_AARCH32_CP15_64 U(0x04)
171 #define ESR_EC_AARCH32_CP14_MR U(0x05)
172 #define ESR_EC_AARCH32_CP14_LS U(0x06)
173 #define ESR_EC_FP_ASIMD U(0x07)
174 #define ESR_EC_AARCH32_CP10_ID U(0x08)
175 #define ESR_EC_PAUTH U(0x09)
176 #define ESR_EC_AARCH32_CP14_64 U(0x0c)
177 #define ESR_EC_BTI U(0x0d)
178 #define ESR_EC_ILLEGAL U(0x0e)
179 #define ESR_EC_AARCH32_SVC U(0x11)
180 #define ESR_EC_AARCH64_SVC U(0x15)
181 #define ESR_EC_AARCH64_SYS U(0x18)
182 #define ESR_EC_ERET U(0x1a)
183 #define ESR_EC_FPAC U(0x1c)
184 #define ESR_EC_IABT_EL0 U(0x20)
185 #define ESR_EC_IABT_EL1 U(0x21)
186 #define ESR_EC_PC_ALIGN U(0x22)
187 #define ESR_EC_DABT_EL0 U(0x24)
188 #define ESR_EC_DABT_EL1 U(0x25)
189 #define ESR_EC_SP_ALIGN U(0x26)
190 #define ESR_EC_AARCH32_FP U(0x28)
191 #define ESR_EC_AARCH64_FP U(0x2c)
192 #define ESR_EC_SERROR U(0x2f)
193 #define ESR_EC_BREAKPT_EL0 U(0x30)
194 #define ESR_EC_BREAKPT_EL1 U(0x31)
195 #define ESR_EC_SOFTSTP_EL0 U(0x32)
196 #define ESR_EC_SOFTSTP_EL1 U(0x33)
197 #define ESR_EC_WATCHPT_EL0 U(0x34)
198 #define ESR_EC_WATCHPT_EL1 U(0x35)
199 #define ESR_EC_AARCH32_BKPT U(0x38)
200 #define ESR_EC_AARCH64_BRK U(0x3c)
203 #define ESR_FSC_MASK U(0x3f)
204 #define ESR_FSC_SIZE_L0 U(0x00)
205 #define ESR_FSC_SIZE_L1 U(0x01)
206 #define ESR_FSC_SIZE_L2 U(0x02)
207 #define ESR_FSC_SIZE_L3 U(0x03)
208 #define ESR_FSC_TRANS_L0 U(0x04)
209 #define ESR_FSC_TRANS_L1 U(0x05)
210 #define ESR_FSC_TRANS_L2 U(0x06)
211 #define ESR_FSC_TRANS_L3 U(0x07)
212 #define ESR_FSC_ACCF_L1 U(0x09)
213 #define ESR_FSC_ACCF_L2 U(0x0a)
214 #define ESR_FSC_ACCF_L3 U(0x0b)
215 #define ESR_FSC_PERMF_L1 U(0x0d)
216 #define ESR_FSC_PERMF_L2 U(0x0e)
217 #define ESR_FSC_PERMF_L3 U(0x0f)
218 #define ESR_FSC_SEA_NTT U(0x10)
219 #define ESR_FSC_TAG_CHECK U(0x11)
220 #define ESR_FSC_SEA_TT_SUB_L2 U(0x12)
221 #define ESR_FSC_SEA_TT_SUB_L1 U(0x13)
222 #define ESR_FSC_SEA_TT_L0 U(0x14)
223 #define ESR_FSC_SEA_TT_L1 U(0x15)
224 #define ESR_FSC_SEA_TT_L2 U(0x16)
225 #define ESR_FSC_SEA_TT_L3 U(0x17)
226 #define ESR_FSC_ALIGN U(0x21)
231 #define CPACR_EL1_FPEN_SHIFT U(20)
232 #define CPACR_EL1_FPEN_MASK U(0x3)
233 #define CPACR_EL1_FPEN_NONE U(0x0)
234 #define CPACR_EL1_FPEN_EL1 U(0x1)
235 #define CPACR_EL1_FPEN_EL0EL1 U(0x3)
241 #define PAR_PA_SHIFT U(12)
244 #define TLBI_VA_SHIFT U(12)
245 #define TLBI_ASID_SHIFT U(48)
246 #define TLBI_ASID_MASK U(0xff)
252 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
253 #define FEAT_MTE_NOT_IMPLEMENTED U(0x0)
254 #define FEAT_MTE_IMPLEMENTED U(0x1)
255 #define FEAT_MTE2_IMPLEMENTED U(0x2)
256 #define FEAT_MTE3_IMPLEMENTED U(0x3)
261 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
262 #define FEAT_PAN_NOT_IMPLEMENTED U(0x0)
263 #define FEAT_PAN_IMPLEMENTED U(0x1)
264 #define FEAT_PAN2_IMPLEMENTED U(0x2)
265 #define FEAT_PAN3_IMPLEMENTED U(0x3)
267 #define ID_AA64ISAR1_GPI_SHIFT U(28)
268 #define ID_AA64ISAR1_GPI_MASK U(0xf)
269 #define ID_AA64ISAR1_GPI_NI U(0x0)
270 #define ID_AA64ISAR1_GPI_IMP_DEF U(0x1)
272 #define ID_AA64ISAR1_GPA_SHIFT U(24)
273 #define ID_AA64ISAR1_GPA_MASK U(0xf)
274 #define ID_AA64ISAR1_GPA_NI U(0x0)
275 #define ID_AA64ISAR1_GPA_ARCHITECTED U(0x1)
277 #define ID_AA64ISAR1_API_SHIFT U(8)
278 #define ID_AA64ISAR1_API_MASK U(0xf)
279 #define ID_AA64ISAR1_API_NI U(0x0)
280 #define ID_AA64ISAR1_API_IMP_DEF U(0x1)
281 #define ID_AA64ISAR1_API_IMP_DEF_EPAC U(0x2)
282 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 U(0x3)
283 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC U(0x4)
284 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB U(0x5)
286 #define ID_AA64ISAR1_APA_SHIFT U(4)
287 #define ID_AA64ISAR1_APA_MASK U(0xf)
288 #define ID_AA64ISAR1_APA_NI U(0x0)
289 #define ID_AA64ISAR1_APA_ARCHITECTED U(0x1)
290 #define ID_AA64ISAR1_APA_ARCH_EPAC U(0x2)
291 #define ID_AA64ISAR1_APA_ARCH_EPAC2 U(0x3)
292 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC U(0x4)
293 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB U(0x5)
295 #define ID_MMFR3_EL1_PAN_SHIFT U(16)
311 #define ID_AA64ISAR0_SHA2_SHIFT U(12)
312 #define ID_AA64ISAR0_SHA2_FEAT_SHA256 U(1)
313 #define ID_AA64ISAR0_SHA2_FEAT_SHA512 U(2)