Lines Matching refs:U
14 #define MIDR_PRIMARY_PART_NUM_SHIFT U(4)
15 #define MIDR_PRIMARY_PART_NUM_WIDTH U(12)
18 #define MIDR_IMPLEMENTER_SHIFT U(24)
19 #define MIDR_IMPLEMENTER_WIDTH U(8)
21 #define MIDR_IMPLEMENTER_ARM U(0x41)
23 #define MIDR_VARIANT_SHIFT U(20)
24 #define MIDR_VARIANT_WIDTH U(4)
27 #define MIDR_REVISION_SHIFT U(0)
28 #define MIDR_REVISION_WIDTH U(4)
31 #define CORTEX_A5_PART_NUM U(0xC05)
32 #define CORTEX_A7_PART_NUM U(0xC07)
33 #define CORTEX_A8_PART_NUM U(0xC08)
34 #define CORTEX_A9_PART_NUM U(0xC09)
35 #define CORTEX_A15_PART_NUM U(0xC0F)
36 #define CORTEX_A17_PART_NUM U(0xC0E)
37 #define CORTEX_A57_PART_NUM U(0xD07)
38 #define CORTEX_A72_PART_NUM U(0xD08)
39 #define CORTEX_A73_PART_NUM U(0xD09)
40 #define CORTEX_A75_PART_NUM U(0xD0A)
41 #define CORTEX_A65_PART_NUM U(0xD06)
42 #define CORTEX_A65AE_PART_NUM U(0xD43)
43 #define CORTEX_A76_PART_NUM U(0xD0B)
44 #define CORTEX_A76AE_PART_NUM U(0xD0E)
45 #define CORTEX_A77_PART_NUM U(0xD0D)
46 #define CORTEX_A78_PART_NUM U(0xD41)
47 #define CORTEX_A78AE_PART_NUM U(0xD42)
48 #define CORTEX_A78C_PART_NUM U(0xD4B)
49 #define CORTEX_A710_PART_NUM U(0xD47)
50 #define CORTEX_X1_PART_NUM U(0xD44)
51 #define CORTEX_X2_PART_NUM U(0xD48)
52 #define NEOVERSE_E1_PART_NUM U(0xD4A)
53 #define NEOVERSE_N1_PART_NUM U(0xD0C)
54 #define NEOVERSE_N2_PART_NUM U(0xD49)
55 #define NEOVERSE_V1_PART_NUM U(0xD40)
58 #define MPIDR_AFFINITY_BITS U(8)
60 #define MPIDR_AFF0_SHIFT U(0)
62 #define MPIDR_AFF1_SHIFT U(8)
64 #define MPIDR_AFF2_SHIFT U(16)
66 #define MPIDR_AFF3_SHIFT U(32)
69 #define MPIDR_MT_SHIFT U(24)
89 #define CLIDR_LOUIS_SHIFT U(21)
90 #define CLIDR_LOC_SHIFT U(24)
91 #define CLIDR_FIELD_WIDTH U(3)
94 #define CSSELR_LEVEL_SHIFT U(1)
97 #define CTR_CWG_SHIFT U(24)
98 #define CTR_CWG_MASK U(0xf)
99 #define CTR_ERG_SHIFT U(20)
100 #define CTR_ERG_MASK U(0xf)
101 #define CTR_DMINLINE_SHIFT U(16)
102 #define CTR_DMINLINE_WIDTH U(4)
104 #define CTR_L1IP_SHIFT U(14)
105 #define CTR_L1IP_MASK U(0x3)
106 #define CTR_IMINLINE_SHIFT U(0)
107 #define CTR_IMINLINE_MASK U(0xf)
108 #define CTR_WORD_SIZE U(4)
110 #define ARM32_CPSR_MODE_MASK U(0x1f)
111 #define ARM32_CPSR_MODE_USR U(0x10)
112 #define ARM32_CPSR_MODE_FIQ U(0x11)
113 #define ARM32_CPSR_MODE_IRQ U(0x12)
114 #define ARM32_CPSR_MODE_SVC U(0x13)
115 #define ARM32_CPSR_MODE_MON U(0x16)
116 #define ARM32_CPSR_MODE_ABT U(0x17)
117 #define ARM32_CPSR_MODE_UND U(0x1b)
118 #define ARM32_CPSR_MODE_SYS U(0x1f)
121 #define ARM32_CPSR_F_SHIFT U(6)
128 #define ARM32_CPSR_IT_MASK1 U(0x06000000)
129 #define ARM32_CPSR_IT_MASK2 U(0x0000fc00)
269 return (read_id_aa64isar1_el1() & mask) != 0U; in feat_pauth_is_implemented()