Lines Matching refs:U
40 #define TZC400_REG_SIZE U(0x1000)
42 #define BUILD_CONFIG_OFF U(0x000)
43 #define ACTION_OFF U(0x004)
44 #define LOCKDOWN_RANGE_OFF U(0x008)
45 #define LOCKDOWN_SELECT_OFF U(0x00C)
46 #define INT_STATUS U(0x010)
47 #define INT_CLEAR U(0x014)
49 #define FAIL_ADDRESS_LOW_OFF U(0x020)
50 #define FAIL_ADDRESS_HIGH_OFF U(0x024)
51 #define FAIL_CONTROL_OFF U(0x028)
52 #define FAIL_ID U(0x02c)
54 #define SPECULATION_CTRL_OFF U(0x030)
55 #define SECURITY_INV_EN_OFF U(0x034)
57 #define REGION_SETUP_LOW_OFF(n) (U(0x100) + (n) * U(0x10))
58 #define REGION_SETUP_HIGH_OFF(n) (U(0x104) + (n) * U(0x10))
59 #define REGION_ATTRIBUTES_OFF(n) (U(0x108) + (n) * U(0x10))
62 #define PID0_OFF U(0xfe0)
63 #define PID1_OFF U(0xfe4)
64 #define PID2_OFF U(0xfe8)
65 #define PID3_OFF U(0xfec)
66 #define PID4_OFF U(0xfd0)
67 #define CID0_OFF U(0xff0)
68 #define CID1_OFF U(0xff4)
69 #define CID2_OFF U(0xff8)
70 #define CID3_OFF U(0xffc)
72 #define BUILD_CONFIG_AW_SHIFT U(8)
73 #define BUILD_CONFIG_AW_MASK U(0x3f)
74 #define BUILD_CONFIG_NR_SHIFT U(0)
75 #define BUILD_CONFIG_NR_MASK U(0xf)
77 #define ACTION_RV_SHIFT U(0)
78 #define ACTION_RV_MASK U(0x3)
79 #define ACTION_RV_LOWOK U(0x0)
80 #define ACTION_RV_LOWERR U(0x1)
81 #define ACTION_RV_HIGHOK U(0x2)
82 #define ACTION_RV_HIGHERR U(0x3)
88 #define INT_STATUS_OVERRUN_SHIFT U(1)
89 #define INT_STATUS_OVERRUN_MASK U(0x1)
90 #define INT_STATUS_STATUS_SHIFT U(0)
91 #define INT_STATUS_STATUS_MASK U(0x1)
93 #define INT_CLEAR_CLEAR_SHIFT U(0)
94 #define INT_CLEAR_CLEAR_MASK U(0x1)
96 #define TZC380_COMPONENT_ID U(0xb105f00d)
97 #define TZC380_PERIPH_ID_LOW U(0x001bb380)
98 #define TZC380_PERIPH_ID_HIGH U(0x00000004)
129 #define TZC_ATTR_SP_SHIFT U(28)
139 #define TZC_REGION_SIZE_32K U(0xe)
140 #define TZC_REGION_SIZE_64K U(0xf)
141 #define TZC_REGION_SIZE_128K U(0x10)
142 #define TZC_REGION_SIZE_256K U(0x11)
143 #define TZC_REGION_SIZE_512K U(0x12)
144 #define TZC_REGION_SIZE_1M U(0x13)
145 #define TZC_REGION_SIZE_2M U(0x14)
146 #define TZC_REGION_SIZE_4M U(0x15)
147 #define TZC_REGION_SIZE_8M U(0x16)
148 #define TZC_REGION_SIZE_16M U(0x17)
149 #define TZC_REGION_SIZE_32M U(0x18)
150 #define TZC_REGION_SIZE_64M U(0x19)
151 #define TZC_REGION_SIZE_128M U(0x1a)
152 #define TZC_REGION_SIZE_256M U(0x1b)
153 #define TZC_REGION_SIZE_512M U(0x1c)
154 #define TZC_REGION_SIZE_1G U(0x1d)
155 #define TZC_REGION_SIZE_2G U(0x1e)
156 #define TZC_REGION_SIZE_4G U(0x1f)
157 #define TZC_REGION_SIZE_8G U(0x20)
158 #define TZC_REGION_SIZE_16G U(0x21)
159 #define TZC_REGION_SIZE_32G U(0x22)
160 #define TZC_REGION_SIZE_64G U(0x23)
161 #define TZC_REGION_SIZE_128G U(0x24)
162 #define TZC_REGION_SIZE_256G U(0x25)
163 #define TZC_REGION_SIZE_512G U(0x26)
164 #define TZC_REGION_SIZE_1T U(0x27)
165 #define TZC_REGION_SIZE_2T U(0x28)
166 #define TZC_REGION_SIZE_4T U(0x29)
167 #define TZC_REGION_SIZE_8T U(0x2a)
168 #define TZC_REGION_SIZE_16T U(0x2b)
169 #define TZC_REGION_SIZE_32T U(0x2c)
170 #define TZC_REGION_SIZE_64T U(0x2d)
171 #define TZC_REGION_SIZE_128T U(0x2e)
172 #define TZC_REGION_SIZE_256T U(0x2f)
173 #define TZC_REGION_SIZE_512T U(0x30)
174 #define TZC_REGION_SIZE_1P U(0x31)
175 #define TZC_REGION_SIZE_2P U(0x32)
176 #define TZC_REGION_SIZE_4P U(0x33)
177 #define TZC_REGION_SIZE_8P U(0x34)
178 #define TZC_REGION_SIZE_16P U(0x35)
179 #define TZC_REGION_SIZE_32P U(0x36)
180 #define TZC_REGION_SIZE_64P U(0x37)
181 #define TZC_REGION_SIZE_128P U(0x38)
182 #define TZC_REGION_SIZE_256P U(0x39)
183 #define TZC_REGION_SIZE_512P U(0x3a)
184 #define TZC_REGION_SIZE_1E U(0x3b)
185 #define TZC_REGION_SIZE_2E U(0x3c)
186 #define TZC_REGION_SIZE_4E U(0x3d)
187 #define TZC_REGION_SIZE_8E U(0x3e)
188 #define TZC_REGION_SIZE_16E U(0x3f)
190 #define TZC_REGION_SIZE_SHIFT U(0x1)
194 #define TZC_SUBREGION_DIS_SHIFT U(8)
200 #define TZC_ATTR_REGION_EN_SHIFT U(0x0)
201 #define TZC_ATTR_REGION_EN_MASK U(0x1)
204 #define TZC_ATTR_REGION_ENABLE U(0x1)
205 #define TZC_ATTR_REGION_DISABLE U(0x0)