plat-stm32mp1: chip and STM32MP15 platform identification

New platform function to get the chip identification using
DBGMCU SoC register.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>

plat-stm32mp1: chip and STM32MP15 platform identification

New platform function to get the chip identification using
DBGMCU SoC register.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: retrieve chip id from syscfg

Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.

Use the chip id to dynamically detect the CRYPTO hardware
support, the se

plat-stm32mp1: retrieve chip id from syscfg

Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.

Use the chip id to dynamically detect the CRYPTO hardware
support, the second CPU core, and CPU OPP.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_tamp: configure the backup registers when driver is probing

Update the driver to be able to configure the backup registers when
the driver is probing and remove call to stm32_tamp_set

drivers: stm32_tamp: configure the backup registers when driver is probing

Update the driver to be able to configure the backup registers when
the driver is probing and remove call to stm32_tamp_set_secure_bkpregs()
in plat-stm32mp1 main.c.

Remove old implementation of stm32_bkpregs_conf structure and rename
stm32_bkpregs_conf_new to stm32_bkpregs_conf.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: define STM32MP13 SRAMs and STM32MP15 RETRAM

Define some platform internal RAMs base address and sizes for STM32MP13
and STM32MP15 SoCs.

Signed-off-by: Etienne Carriere <etienne.carri

plat-stm32mp1: define STM32MP13 SRAMs and STM32MP15 RETRAM

Define some platform internal RAMs base address and sizes for STM32MP13
and STM32MP15 SoCs.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp1: add stm32mp1_pa_or_sram_alias_pa()

Add stm32mp1_pa_or_sram_alias_pa() helper function to ease handling
SRAMx physical addresses that have aliases on STM32MP15 SoC.

Signed-off-by: Eti

plat-stm32mp1: add stm32mp1_pa_or_sram_alias_pa()

Add stm32mp1_pa_or_sram_alias_pa() helper function to ease handling
SRAMx physical addresses that have aliases on STM32MP15 SoC.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_etzpc: new driver to use firewall API

Implement stm32_etzpc.c driver in the firewall driver directory.
Use the new firewall API to populate the firewall bus and register
the ETZPC as

drivers: stm32_etzpc: new driver to use firewall API

Implement stm32_etzpc.c driver in the firewall driver directory.
Use the new firewall API to populate the firewall bus and register
the ETZPC as a firewall provider.

Implement a driver specific firewall bus probe that will
only probe secure peripherals and implement firewall exceptions for
which no firewall operations will be done when CFG_INSECURE is set.
This allows, for example, to share a console with the non-secure world
for development purposes.

The ETZPC driver register the following ops:
-set_conf
-acquire_access
-acquire_memory_access

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
AP

plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
API functions. This configuration must be appleid at boot time and
when resuming from a system low power state.

This configuration depends on VDD voltage level. It can protected by
a OTP bit (HW2 bit 13) described in the chip reference manual for when
VDD is supplied with a voltage below 2.5V. As stated in the chip
reference manual, enabling HSLV mode with a VDD voltage level above
2.7V may be destructive hence the driver panics in such case.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: shared_resources: consider SRAMs

Adds SRAMs to the STM32MP15 shared resources.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.ca

plat-stm32mp1: shared_resources: consider SRAMs

Adds SRAMs to the STM32MP15 shared resources.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: scmi_server: support use of OP-TEE shared memory

Updates scmi_server configuration and implementation for the platform
to use OP-TEE native shared memory instead of device memory mapp

plat-stm32mp1: scmi_server: support use of OP-TEE shared memory

Updates scmi_server configuration and implementation for the platform
to use OP-TEE native shared memory instead of device memory mapped
SRAM for SCMI messages transfer. With this change, configuring
CFG_STM32MP1_SCMI_SHM_BASE to 0 allows such setup.

This change moves registration of CFG_STM32MP1_SCMI_SHM_BASE as
non-secure mapped device memory from main.c to scmi_server.c
to have all SCMI related platform resources defined from that
source file.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: support 32bit MMU

Updates CFG_TEE_RAM_VA_SIZE default value and MAX_XLAT_TABLES when
32bit-MMU mapping is used instead of LPAE and default disable LPAE
for STM32MP15 with pager.

plat-stm32mp1: conf: support 32bit MMU

Updates CFG_TEE_RAM_VA_SIZE default value and MAX_XLAT_TABLES when
32bit-MMU mapping is used instead of LPAE and default disable LPAE
for STM32MP15 with pager. This setup optimizes pager resident memory
by about 4kB (1 physical page) in current platform default configuration.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: fix SYSRAM size on stm32mp13 variants

Fixes internal RAM SYSRAM size on STM32MP13 variants that is 128kB.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien

plat-stm32mp1: fix SYSRAM size on stm32mp13 variants

Fixes internal RAM SYSRAM size on STM32MP13 variants that is 128kB.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_bsec: use DT NVMEM layout API

Uses OTP definition in the device tree, by using the function
stm32_bsec_find_otp_in_nvmem_layout() and removes the
hardcoded OTP index in platform confi

drivers: stm32_bsec: use DT NVMEM layout API

Uses OTP definition in the device tree, by using the function
stm32_bsec_find_otp_in_nvmem_layout() and removes the
hardcoded OTP index in platform config.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: remove stm32mp_is_closed_device()

Removes stm32mp_is_closed_device() platform function and related
resources as it is superseded by BSEC driver API function
stm32_bsec_get_state().

S

plat-stm32mp1: remove stm32mp_is_closed_device()

Removes stm32mp_is_closed_device() platform function and related
resources as it is superseded by BSEC driver API function
stm32_bsec_get_state().

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_bsec: update for stm32mp13

Adds support for stm32mp13x platforms in BSEC driver.
Permanent lock status is updated without reset.

Signed-off-by: Patrick Delaunay <patrick.delaunay@fos

drivers: stm32_bsec: update for stm32mp13

Adds support for stm32mp13x platforms in BSEC driver.
Permanent lock status is updated without reset.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_bsec: add new generic interfaces

Exports generic functions to retrieve the BSEC state and check
if a fuse can be read depending on the BSEC current state.
Adds some robustness in the

drivers: stm32_bsec: add new generic interfaces

Exports generic functions to retrieve the BSEC state and check
if a fuse can be read depending on the BSEC current state.
Adds some robustness in the driver to enforce security when
trying to access a fuse.

It is a preliminary step for BSEC PTA introduction.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: add support for i2c5 bus

This allows stm32_i2c driver to properly initialize and use
i2c5 bus on stm32mp15 SoC.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Igor O

plat-stm32mp1: add support for i2c5 bus

This allows stm32_i2c driver to properly initialize and use
i2c5 bus on stm32mp15 SoC.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: define specific STM32MP13 peripheral addresses

Some peripheral addresses differ from STM32MP15 to STM32MP13.
This change adds support for those differences.

Signed-off-by: Gatien Che

plat-stm32mp1: define specific STM32MP13 peripheral addresses

Some peripheral addresses differ from STM32MP15 to STM32MP13.
This change adds support for those differences.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: add watchdog platform functions

Add the platform function to retrieve the watchdog OTP
configuration. Register the debug function to dump
register in case of watchdog detected event.

plat-stm32mp1: add watchdog platform functions

Add the platform function to retrieve the watchdog OTP
configuration. Register the debug function to dump
register in case of watchdog detected event.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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plat-stm32mp1: define backup register secure accesses

Implements access permissions for stm32mp1 backup registers accesses.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: E

plat-stm32mp1: define backup register secure accesses

Implements access permissions for stm32mp1 backup registers accesses.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: simplify device memory mapping

Register device memory by cluster range rather than by device interface
as the later is likely to grow as new devices are added whereas the
overall stat

plat-stm32mp1: simplify device memory mapping

Register device memory by cluster range rather than by device interface
as the later is likely to grow as new devices are added whereas the
overall static mapped may not change.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: enable IO compensation at boot time

Implement platform functions stm32mp_syscfg_enable_io_compensation()
and stm32mp_syscfg_disable_io_compensation() to enable/disable
STM23MP1 IO com

plat-stm32mp1: enable IO compensation at boot time

Implement platform functions stm32mp_syscfg_enable_io_compensation()
and stm32mp_syscfg_disable_io_compensation() to enable/disable
STM23MP1 IO compensation. Enable IO compensation when platform boots.

This change defines SYSCFG clock that is needed and moves definition
of the RCC compatible string DT_RCC_CLK_COMPAT to RCC header file so
that it can be shared with stm32mp1_syscfg.c.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: check TZC400 configuration

Core checks TZC400 configuration during initialization to ensure
DDR firewall expectations are satisfied.

Signed-off-by: Etienne Carriere <etienne.carriere

plat-stm32mp1: check TZC400 configuration

Core checks TZC400 configuration during initialization to ensure
DDR firewall expectations are satisfied.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: assign last 4kB of sysram as shared memory

Allow the last 4kByte of stm32mp1 SYSRAM internal RAM to be
assigned to non-secure world when used as SCMI shared memory.
ETZPC memory firew

plat-stm32mp1: assign last 4kB of sysram as shared memory

Allow the last 4kByte of stm32mp1 SYSRAM internal RAM to be
assigned to non-secure world when used as SCMI shared memory.
ETZPC memory firewall is configured accordingly from service
late initialization level as ETPCZ driver is initialized from
service init level when embedded BTD support is enabled.

Platform configuration switches CFG_STM32MP1_SCMI_SHM_BASE and
CFG_STM32MP1_SCMI_SHM_SIZE are used to define the SCMI shared
memory location.

Compilation asserts that if CFG_TZSRAM_START is define inside SYSRAM
then it fully resides inside the secure SYSRAM area as per SoC ETZPC
implementation that mandates the non-secure SYSRAM to be above (higher
address) the secure SYSRAM.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: enable dynamic shared memory

Register dynamic shared memory allowed by the platform that is
the DRAM address ranges below and above the secure DRAM (TZDRAM).

Signed-off-by: Etienne C

plat-stm32mp1: enable dynamic shared memory

Register dynamic shared memory allowed by the platform that is
the DRAM address ranges below and above the secure DRAM (TZDRAM).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: shres: registering shared resources

This change implements a driver for the stm32mp1 resources that may
be assigned to either secure or non-secure worlds upon the platform
configuration.

stm32mp1: shres: registering shared resources

This change implements a driver for the stm32mp1 resources that may
be assigned to either secure or non-secure worlds upon the platform
configuration.

Other drivers shall register their resources (when applicable) using
the API functions stm32mp_register_{secure|non_secure}_periph*():
- stm32mp_register_*_periph() registers a resource from its
platform ID.
- stm32mp_register_*_periph_iomem() registers a resource from its
IOMEM base address.
- stm32mp_register_*_periph_gpio() registers a resource from its
GPIO reference, bank and position.

Shared resource driver exports some APIs to query a resource
registration state, stm32mp_periph_is_*(),
stm32mp_gpio_bank_is_*(), stm32mp_clock_is_*().

The driver saves the peripheral assignation. The API does not
allow peripherals to change state at runtime. Moverover, to
prevent testing a resource status before it is registered,
the first query on a resource state locks further registering.
Later attempt to register a peripheral will panic the core.

Resources are either secure on non-secure but clock that maybe
shared in which case it will be assigned to the secure world but
a platform service will allow non-secure to access the resource
(i.e. enable/disable the clock). Note such service is out of the
scope of this change, yet this explains API stm32mp_clock_is_shared().

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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