1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 32 13 14 /* Translation table */ 15 #ifdef CFG_WITH_LPAE 16 #define MAX_XLAT_TABLES 4 17 #else 18 #define MAX_XLAT_TABLES 8 19 #endif 20 21 /* SoC interface registers base address ranges */ 22 #define APB1_BASE 0x40000000 23 #define APB1_SIZE 0x0001d000 24 #define APB2_BASE 0x44000000 25 #define APB2_SIZE 0x00014000 26 #define APB3_BASE 0x50020000 27 #define APB3_SIZE 0x0000b000 28 #define APB4_BASE 0x5a000000 29 #define APB4_SIZE 0x00008000 30 #define APB5_BASE 0x5c000000 31 #define APB5_SIZE 0x0000b000 32 #ifdef CFG_STM32MP13 33 #define APB6_BASE 0x4c000000 34 #define APB6_SIZE 0x0000d000 35 #endif 36 37 #define AHB4_BASE 0x50000000 38 #define AHB4_SIZE 0x00020000 39 #ifdef CFG_STM32MP13 40 #define AHB5_BASE 0x54000000 41 #define AHB5_SIZE 0x00008000 42 #endif 43 #ifdef CFG_STM32MP15 44 #define AHB5_BASE 0x54000000 45 #define AHB5_SIZE 0x00005000 46 #endif 47 48 /* SoC interface registers base address */ 49 #define BSEC_BASE 0x5c005000 50 #define ETZPC_BASE 0x5c007000 51 #define CRYP1_BASE 0x54001000 52 #define DBGMCU_BASE 0x50081000 53 #define DDR_BASE 0xc0000000ul 54 #define GIC_BASE 0xa0021000ul 55 #define GPIOA_BASE 0x50002000 56 #define GPIOB_BASE 0x50003000 57 #define GPIOC_BASE 0x50004000 58 #define GPIOD_BASE 0x50005000 59 #define GPIOE_BASE 0x50006000 60 #define GPIOF_BASE 0x50007000 61 #define GPIOG_BASE 0x50008000 62 #define GPIOH_BASE 0x50009000 63 #define GPIOI_BASE 0x5000a000 64 #define GPIOJ_BASE 0x5000b000 65 #define GPIOK_BASE 0x5000c000 66 #define GPIOZ_BASE 0x54004000 67 #define HASH1_BASE 0x54002000 68 #define I2C4_BASE 0x5c002000 69 #define I2C5_BASE 0x40015000 70 #define I2C6_BASE 0x5c009000 71 #define IWDG1_BASE 0x5c003000 72 #define IWDG2_BASE 0x5a002000 73 #define PWR_BASE 0x50001000 74 #define RCC_BASE 0x50000000 75 #ifdef CFG_STM32MP13 76 #define RNG1_BASE 0x54004000 77 #endif 78 #ifdef CFG_STM32MP15 79 #define RNG1_BASE 0x54003000 80 #endif 81 #define RTC_BASE 0x5c004000 82 #define SPI6_BASE 0x5c001000 83 #define SYSCFG_BASE 0x50020000 84 #ifdef CFG_STM32MP13 85 #define SYSRAM_BASE 0x2ffe0000 86 #endif 87 #ifdef CFG_STM32MP15 88 #define SYSRAM_BASE 0x2ffc0000 89 #endif 90 #define TAMP_BASE 0x5c00a000 91 #define TZC_BASE 0x5c006000 92 #ifdef CFG_STM32MP13 93 #define UART1_BASE 0x4c000000 94 #define UART2_BASE 0x4c001000 95 #endif 96 #ifdef CFG_STM32MP15 97 #define UART1_BASE 0x5c000000 98 #define UART2_BASE 0x4000e000 99 #endif 100 #define UART3_BASE 0x4000f000 101 #define UART4_BASE 0x40010000 102 #define UART5_BASE 0x40011000 103 #define UART6_BASE 0x44003000 104 #define UART7_BASE 0x40018000 105 #define UART8_BASE 0x40019000 106 107 #define ROM_BASE 0 108 #define ROM_SIZE 0x20000 109 110 /* Console configuration */ 111 #define STM32MP1_DEBUG_USART_BASE UART4_BASE 112 #define GIC_SPI_UART4 84 113 114 #define CONSOLE_UART_BASE STM32MP1_DEBUG_USART_BASE 115 #define CONSOLE_UART_SIZE 1024 116 117 /* BSEC OTP resources */ 118 #define STM32MP1_OTP_MAX_ID 0x5FU 119 #define STM32MP1_UPPER_OTP_START 0x20U 120 121 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 122 123 /* Bit map for BSEC word CFG0_OTP */ 124 #ifdef CFG_STM32MP13 125 #define CFG0_OTP_CLOSED_DEVICE U(0x3F) 126 #endif 127 #ifdef CFG_STM32MP15 128 #define CFG0_OTP_CLOSED_DEVICE BIT(6) 129 #endif 130 131 /* Bit map for BSEC word HW2_OTP */ 132 #define HW2_OTP_IWDG_HW_ENABLE_SHIFT U(3) 133 #define HW2_OTP_IWDG_FZ_STOP_SHIFT U(5) 134 #define HW2_OTP_IWDG_FZ_STANDBY_SHIFT U(7) 135 136 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 137 138 /* GIC resources */ 139 #define GIC_SIZE 0x2000 140 #define GICC_OFFSET 0x1000 141 #define GICD_OFFSET 0x0000 142 143 #define GIC_NON_SEC_SGI_0 0 144 #define GIC_SEC_SGI_0 8 145 #define GIC_SEC_SGI_1 9 146 147 #define TARGET_CPU0_GIC_MASK BIT(0) 148 #define TARGET_CPU1_GIC_MASK BIT(1) 149 #define TARGET_CPUS_GIC_MASK GENMASK_32(CFG_TEE_CORE_NB_CORE - 1, 0) 150 151 /* 152 * GPIO banks: 11 non secure banks (A to K) and 1 secure bank (Z) 153 * Bank register's base address is computed from the bank ID listed here. 154 */ 155 #define GPIOS_NSEC_COUNT 11 156 #define GPIOS_NSEC_BASE GPIOA_BASE 157 #define GPIOS_NSEC_SIZE (GPIOS_NSEC_COUNT * SMALL_PAGE_SIZE) 158 159 #define STM32MP1_GPIOZ_MAX_COUNT 1 160 #define STM32MP1_GPIOZ_PIN_MAX_COUNT 8 161 162 #define GPIO_BANK_OFFSET 0x1000U 163 164 /* Bank IDs used in GPIO driver API */ 165 #define GPIO_BANK_A 0U 166 #define GPIO_BANK_B 1U 167 #define GPIO_BANK_C 2U 168 #define GPIO_BANK_D 3U 169 #define GPIO_BANK_E 4U 170 #define GPIO_BANK_F 5U 171 #define GPIO_BANK_G 6U 172 #define GPIO_BANK_H 7U 173 #define GPIO_BANK_I 8U 174 #define GPIO_BANK_J 9U 175 #define GPIO_BANK_K 10U 176 #define GPIO_BANK_Z 25U 177 178 /* TAMP resources */ 179 #define TAMP_BKP_REGISTER_OFF 0x100 180 #define TAMP_BKP_REGISTER_COUNT U(32) 181 182 /* TZC resources */ 183 #define STM32MP1_IRQ_TZC 36 184 185 #define STM32MP1_TZC_A7_ID 0 186 #define STM32MP1_TZC_M4_ID 1 187 #define STM32MP1_TZC_LCD_ID 3 188 #define STM32MP1_TZC_GPU_ID 4 189 #define STM32MP1_TZC_MDMA_ID 5 190 #define STM32MP1_TZC_DMA_ID 6 191 #define STM32MP1_TZC_USB_HOST_ID 7 192 #define STM32MP1_TZC_USB_OTG_ID 8 193 #define STM32MP1_TZC_SDMMC_ID 9 194 #define STM32MP1_TZC_ETH_ID 10 195 #define STM32MP1_TZC_DAP_ID 15 196 197 /* USART/UART resources */ 198 #define USART1_BASE UART1_BASE 199 #define USART2_BASE UART2_BASE 200 #define USART3_BASE UART3_BASE 201 #define USART6_BASE UART6_BASE 202 203 /* DBGMCU resources */ 204 #define DBGMCU_IDC U(0x0) 205 #define DBGMCU_IDC_DEV_ID_MASK GENMASK_32(11, 0) 206 #define DBGMCU_IDC_REV_ID_MASK GENMASK_32(31, 16) 207 #define DBGMCU_IDC_REV_ID_SHIFT U(16) 208 209 /* SYSRAM layout */ 210 #ifdef CFG_STM32MP13 211 #define SYSRAM_SIZE 0x20000 212 #else /* Assume CFG_STM32MP15 */ 213 #define SYSRAM_SIZE 0x40000 214 #endif 215 #define SYSRAM_NS_SIZE (SYSRAM_SIZE - SYSRAM_SEC_SIZE) 216 217 /* Non-secure SYSRAM must be above (higher addresses) secure SYSRAM */ 218 #define STM32MP1_SCMI_SHM_END (CFG_STM32MP1_SCMI_SHM_BASE + \ 219 CFG_STM32MP1_SCMI_SHM_SIZE) 220 221 #if (CFG_STM32MP1_SCMI_SHM_BASE && \ 222 (CFG_STM32MP1_SCMI_SHM_BASE >= SYSRAM_BASE) && \ 223 (STM32MP1_SCMI_SHM_END <= (SYSRAM_BASE + SYSRAM_SIZE))) 224 #define SYSRAM_SEC_SIZE (CFG_STM32MP1_SCMI_SHM_BASE - SYSRAM_BASE) 225 #else 226 #define SYSRAM_SEC_SIZE SYSRAM_SIZE 227 #endif 228 229 #ifdef CFG_STM32MP15 230 #define SRAM1_BASE 0x30000000 231 #define SRAM2_BASE 0x30020000 232 #define SRAM3_BASE 0x30040000 233 #define SRAM4_BASE 0x30050000 234 /* Alternate SRAM base address possibly used by remoteproc firmware */ 235 #define SRAM1_ALT_BASE 0x10000000 236 #define SRAM2_ALT_BASE 0x10020000 237 #define SRAM3_ALT_BASE 0x10040000 238 #define SRAM4_ALT_BASE 0x10050000 239 240 #define SRAM1_SIZE 0x20000 241 #define SRAM2_SIZE 0x20000 242 #define SRAM3_SIZE 0x10000 243 #define SRAM4_SIZE 0x10000 244 245 #define RETRAM_BASE 0x38000000 246 #define RETRAM_SIZE 0x10000 247 #endif 248 249 #ifdef CFG_STM32MP13 250 /* SRAM layout*/ 251 #define SRAM1_BASE 0x30000000 252 #define SRAM1_SIZE 0x4000 253 #define SRAM2_BASE 0x30004000 254 #define SRAM2_SIZE 0x2000 255 #define SRAM3_BASE 0x30006000 256 #define SRAM3_SIZE 0x2000 257 #endif 258 259 /* SoC part numbers and revisions */ 260 #define STM32MP135C_PART_NB U(0x05010000) 261 #define STM32MP135A_PART_NB U(0x05010001) 262 #define STM32MP133C_PART_NB U(0x050100C0) 263 #define STM32MP133A_PART_NB U(0x050100C1) 264 #define STM32MP131C_PART_NB U(0x050106C8) 265 #define STM32MP131A_PART_NB U(0x050106C9) 266 #define STM32MP135F_PART_NB U(0x05010800) 267 #define STM32MP135D_PART_NB U(0x05010801) 268 #define STM32MP133F_PART_NB U(0x050108C0) 269 #define STM32MP133D_PART_NB U(0x050108C1) 270 #define STM32MP131F_PART_NB U(0x05010EC8) 271 #define STM32MP131D_PART_NB U(0x05010EC9) 272 273 #define STM32MP157C_PART_NB U(0x05000000) 274 #define STM32MP157A_PART_NB U(0x05000001) 275 #define STM32MP153C_PART_NB U(0x05000024) 276 #define STM32MP153A_PART_NB U(0x05000025) 277 #define STM32MP151C_PART_NB U(0x0500002E) 278 #define STM32MP151A_PART_NB U(0x0500002F) 279 #define STM32MP157F_PART_NB U(0x05000080) 280 #define STM32MP157D_PART_NB U(0x05000081) 281 #define STM32MP153F_PART_NB U(0x050000A4) 282 #define STM32MP153D_PART_NB U(0x050000A5) 283 #define STM32MP151F_PART_NB U(0x050000AE) 284 #define STM32MP151D_PART_NB U(0x050000AF) 285 286 #ifdef CFG_STM32MP13 287 #define STM32MP1_CHIP_ID U(0x501) 288 #endif 289 290 #ifdef CFG_STM32MP15 291 #define STM32MP1_CHIP_ID U(0x500) 292 #endif 293 294 #endif /*PLATFORM_CONFIG_H*/ 295