| #
62d8e0e8 |
| 16-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: arm: add guards to sm/psci.h
Adds missing header guards in sm/psci.h.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
2441aaf0 |
| 16-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: arm: add notice to sm/psci.h and sm/std_smc.h
Adds missing notice in sm/psci.h and sm/std_smc.h that was not stated when these header files were initially merged [1]. License is set to BSD-2-C
core: arm: add notice to sm/psci.h and sm/std_smc.h
Adds missing notice in sm/psci.h and sm/std_smc.h that was not stated when these header files were initially merged [1]. License is set to BSD-2-Clause as per OP-TEE OS license model at the time of [1] and up to now. Copyright is set to Linaro as per being the maintainer of OP-TEE.
CC: Peng Fan <peng.fan@nxp.com> Link: https://github.com/OP-TEE/optee_os/commit/319556cdc38514d0261bec0abf87627d0782f8e [1] Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
9daed40c |
| 26-Apr-2021 |
Igor Opaniuk <igor.opaniuk@foundries.io> |
core: arm: sm: upgrade to PSCI 1.1
Add support for new functions, introduced in PSCI v1.1 spec [1] (all are optional): * SYSTEM_RESET2 - extends existing SYSTEM_RESET. It provides
core: arm: sm: upgrade to PSCI 1.1
Add support for new functions, introduced in PSCI v1.1 spec [1] (all are optional): * SYSTEM_RESET2 - extends existing SYSTEM_RESET. It provides architectural reset definitions and vendor-specific resets. * MEM_PROTECT - provides protection against cold reboot attacks, by ensuring that memory is overwritten before it is handed over to an operating system loader. * MEM_PROTECT_CHECK_RANGE - used to check whether a memory range is protected by MEM_PROTECT.
[1] https://developer.arm.com/documentation/den0022/latest/
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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| #
a83bf6de |
| 28-Apr-2021 |
Igor Opaniuk <igor.opaniuk@foundries.io> |
core: arm: sm: replace function ids with hex values
Replace PSCI function id defines with full hex values, so it's easier to validate existing values/add new one from PSCI spec updates.
Reviewed-by
core: arm: sm: replace function ids with hex values
Replace PSCI function id defines with full hex values, so it's easier to validate existing values/add new one from PSCI spec updates.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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| #
4a6784ca |
| 30-Apr-2021 |
Jens Wiklander <jens.wiklander@linaro.org> |
core/arch/arm/include/*.h: use U() for unsigned constants
Updates with the U() macro as described in the recently updated coding guidelines.
Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked
core/arch/arm/include/*.h: use U() for unsigned constants
Updates with the U() macro as described in the recently updated coding guidelines.
Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
fc59f7e5 |
| 02-Jun-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: psci.h: add PSCI_CPU_ON_SMC64
Adds PSCI_CPU_ON_SMC64 which is using the 64-bit calling convention as a complement to define PSCI_CPU_ON using the 32-bit calling convention.
Acked-by: Etienne
core: psci.h: add PSCI_CPU_ON_SMC64
Adds PSCI_CPU_ON_SMC64 which is using the 64-bit calling convention as a complement to define PSCI_CPU_ON using the 32-bit calling convention.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
789e38a6 |
| 06-Nov-2017 |
Zeng Tao <prime.zeng@hisilicon.com> |
core: arm: psci: pass nsec ctx to system_suspend
In the commit 732fc43(core: arm: psci: pass nsec ctx to psci), we have done the job, but we forgot to follow it in the later commit 1d40eb8 (core: ar
core: arm: psci: pass nsec ctx to system_suspend
In the commit 732fc43(core: arm: psci: pass nsec ctx to psci), we have done the job, but we forgot to follow it in the later commit 1d40eb8 (core: arm: sm: add PSCI system suspend), fix it in this patch.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
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| #
b3c4f4f5 |
| 05-Sep-2017 |
Peng Fan <peng.fan@nxp.com> |
core: arm: sm: add psci power state macros
Add PSCI_POWER_STATE_X macros
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carr
core: arm: sm: add psci power state macros
Add PSCI_POWER_STATE_X macros
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
1b181fb2 |
| 12-Sep-2017 |
Peng Fan <peng.fan@nxp.com> |
core: arm: psci: pass nsec ctx to psci
Pass non-secure context to psci functions. When cpu/system suspends, cpu may loose power, so when back to linux from tee, tee needs to return to a linux resume
core: arm: psci: pass nsec ctx to psci
Pass non-secure context to psci functions. When cpu/system suspends, cpu may loose power, so when back to linux from tee, tee needs to return to a linux resume point, not the usual return address after "smc" instruction. So we need to modify the mon_lr value in non-secure context.
Psci runs in monitor mode, sm_get_nsec_ctx can not be used, so pass the non-secure context pointer to the psci suspend function.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
81637626 |
| 10-Jul-2017 |
Joseph Chen <chenjh@rock-chips.com> |
core: arm: sm: add PSCI system suspend
Add __weak property for the function, developers could have their own implementation.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Acked-by: Jerome Fori
core: arm: sm: add PSCI system suspend
Add __weak property for the function, developers could have their own implementation.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
7ce47501 |
| 22-Jun-2017 |
Peng Fan <peng.fan@nxp.com> |
core: arm: psci: add helper functions
Add helper function psci_armv7_cpu_off. This function will be used when use psci to offline a cpu.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Etie
core: arm: psci: add helper functions
Add helper function psci_armv7_cpu_off. This function will be used when use psci to offline a cpu.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
319556cd |
| 11-Jan-2017 |
Peng Fan <peng.fan@nxp.com> |
core: arm: add PSCI support
Introduce basic PSCI support. When CFG_PSCI_ARM32 is defined, PSCI functions will be enabled. Add __weak property for the PSCI functions, developers could have their own
core: arm: add PSCI support
Introduce basic PSCI support. When CFG_PSCI_ARM32 is defined, PSCI functions will be enabled. Add __weak property for the PSCI functions, developers could have their own implementation.
PSCI is handled in monitor mode, and when finished, directly returns to nsec world.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> [s/psci/PSCI/ in commit log. Rebase on top of master.] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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