1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 */ 5 6 #ifndef __KERNEL_TZ_PROC_DEF_H 7 #define __KERNEL_TZ_PROC_DEF_H 8 9 #include <stdint.h> 10 11 /* 12 * General constants 13 */ 14 15 /* 16 * CP15 Multiprocessor Affinity register (MPIDR) 17 */ 18 #define CP15_CONFIG_CPU_ID_MASK U(0x00000003) 19 #define CPU_ID0 U(0x00000000) 20 #define CPU_ID1 U(0x00000001) 21 22 /* 23 * CP15 Secure configuration register 24 */ 25 #define CP15_CONFIG_NS_MASK U(0x00000001) 26 #define CP15_CONFIG_IRQ_MASK U(0x00000002) 27 #define CP15_CONFIG_FIQ_MASK U(0x00000004) 28 #define CP15_CONFIG_EA_MASK U(0x00000008) 29 #define CP15_CONFIG_FW_MASK U(0x00000010) 30 #define CP15_CONFIG_AW_MASK U(0x00000020) 31 #define CP15_CONFIG_nET_MASK U(0x00000040) 32 33 /* 34 * CP15 Control register 35 */ 36 #define CP15_CONTROL_M_MASK U(0x00000001) 37 #define CP15_CONTROL_C_MASK U(0x00000004) 38 #define CP15_CONTROL_Z_MASK U(0x00000800) 39 #define CP15_CONTROL_I_MASK U(0x00001000) 40 #define CP15_CONTROL_V_MASK U(0x00002000) 41 #define CP15_CONTROL_HA_MASK U(0x00020000) 42 #define CP15_CONTROL_EE_MASK U(0x02000000) 43 #define CP15_CONTROL_NMFI_MASK U(0x08000000) 44 #define CP15_CONTROL_TRE_MASK U(0x10000000) 45 #define CP15_CONTROL_AFE_MASK U(0x20000000) 46 #define CP15_CONTROL_TE_MASK U(0x40000000) 47 48 /* 49 * CP15 Auxiliary Control register 50 */ 51 #define CP15_CONTROL_SMP_MASK U(0x00000040) 52 #define CP15_CONTROL_EXCL_MASK U(0x00000080) 53 54 /* 55 * CP15 Non secure access control register 56 */ 57 #define CP15_NSAC_TL_MASK U(0x10000) 58 #define CP15_NSAC_CL_MASK U(0x20000) 59 #define CP15_NSAC_CPN_MASK U(0x3FFF) 60 61 /* 62 * CP15 Cache register 63 */ 64 #define CP15_CACHE_ADDR_R_BIT U(12) 65 #define CP15_CACHE_ADDR_L_BIT (U(32) - CP15_CACHE_ADDR_R_BIT) 66 #define CP15_CACHE_RESULT_MASK U(0x00000001) 67 68 /* 69 * CP15 TCM register 70 * 71 * ITCM configuration (4kbytes, @0x20100000, enabled) 72 * DTCM configuration (4kbytes, @0x20101000, enabled) 73 */ 74 #define CP15_TCM_ENABLE_MASK U(0x00000001) 75 #define CP15_TCM_INSTR_TCM U(0x2010000C) 76 #define CP15_TCM_DATA_TCM U(0x2010100C) 77 78 /* 79 * CP15 cache lockdown register 80 * 81 * ITCM configuration (4kbytes, @0x20100000, enabled) 82 * DTCM configuration (4kbytes, @0x20101000, enabled) 83 */ 84 #define CP15_CACHE_LOCK_ALLWAYS_MASK U(0x0000000F) 85 86 /* 87 * CP15 cache cleaning constant definition 88 */ 89 /* start of line number field offset in way/index format */ 90 #define LINE_FIELD_OFFSET U(5) 91 /* Warning: this assumes a 256 lines/way cache (32kB cache) */ 92 #define LINE_FIELD_OVERFLOW U(13) 93 /* start of way number field offset in way/index format */ 94 #define WAY_FIELD_OFFSET U(30) 95 96 #endif /*__KERNEL_TZ_PROC_DEF_H*/ 97