core: change get_core_pos_mpidr() to support hypervisor

The secure hypervisor, such as Hafnium, is expected to manipulate
MPIDR_EL1 to indicate a VCPU ID.

This commit makes get_core_pos_mpidr() not

core: change get_core_pos_mpidr() to support hypervisor

The secure hypervisor, such as Hafnium, is expected to manipulate
MPIDR_EL1 to indicate a VCPU ID.

This commit makes get_core_pos_mpidr() not calculate a CPU ID
using the affinity bitfields of MPIDR_EL1 when there is a hypervisor
in SEL2.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>

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core: arm: add helper functions for checking CE support

Add helper functions for checking implementation of SHA1, SHA256,
SHA512, SHA3, SM3, SM4 instructions.

Acked-by: Etienne Carriere <etienne.ca

core: arm: add helper functions for checking CE support

Add helper functions for checking implementation of SHA1, SHA256,
SHA512, SHA3, SM3, SM4 instructions.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add check in aarch32 for feat_crc32_implemented()

Add support for checking CRC32 HW instruction in aarch32.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wik

core: arm: add check in aarch32 for feat_crc32_implemented()

Add support for checking CRC32 HW instruction in aarch32.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: rewrite feat_crc32_implemented()

Rewrite check in feat_crc32_implementedfor for ARM64.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklande

core: arm: rewrite feat_crc32_implemented()

Rewrite check in feat_crc32_implementedfor for ARM64.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add masks for ID_ISAR5_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_ISAR5_EL1 register:

Algo Bits
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [1

core: arm: add masks for ID_ISAR5_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_ISAR5_EL1 register:

Algo Bits
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [11:8]
AES - [7:4]

For additional details check ARM Architecture Reference Manual
for ARMv8-A architecture profile.
D10.2.66 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: prefix header file guard names with __

Improves header files guard names consistency by using a __ prefix
where missing.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by:

core: prefix header file guard names with __

Improves header files guard names consistency by using a __ prefix
where missing.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm.h: Add MPIDR definition for aff3 field

Adds define MPIDR_AFF3_SHIFT and MPIDR_AFF3_MASK.
And extend MPIDR_AFFLVL_MASK to 64 bits to support
the 64-bit MPIDR_EL1 on aarch64.

Signed-off-by:

core: arm.h: Add MPIDR definition for aff3 field

Adds define MPIDR_AFF3_SHIFT and MPIDR_AFF3_MASK.
And extend MPIDR_AFFLVL_MASK to 64 bits to support
the 64-bit MPIDR_EL1 on aarch64.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: add feat_pan_implemented()

Adds the helper function feat_pan_implemented() to extract the
implemented PAN version. No version is 0 so this function can be used
tested as a boolean too.

S

core: arm: add feat_pan_implemented()

Adds the helper function feat_pan_implemented() to extract the
implemented PAN version. No version is 0 so this function can be used
tested as a boolean too.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm64: add CRC32 HW support discovery

Add helper function to check if the CRC32 instructions are implemented
by the PE.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: J

core: arm64: add CRC32 HW support discovery

Add helper function to check if the CRC32 instructions are implemented
by the PE.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: arm64: add MTE bits for ID_AA64PFR1

Adds fields in register ID_AA64PFR1 to report the presence of Memory
Tagging Extension (MTE).

Adds feat_mte_implemented() to report which MTE feature flav

core: arm64: add MTE bits for ID_AA64PFR1

Adds fields in register ID_AA64PFR1 to report the presence of Memory
Tagging Extension (MTE).

Adds feat_mte_implemented() to report which MTE feature flavor is
supported.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add arm cortex and neoverse CPU part numbers

Adds part numbers for a few Arm Cortex and Neoverse CPUs. Also adds
defines helping to extract Variant and Revision from MIDR or MIDR_EL1.

Acked-b

core: add arm cortex and neoverse CPU part numbers

Adds part numbers for a few Arm Cortex and Neoverse CPUs. Also adds
defines helping to extract Variant and Revision from MIDR or MIDR_EL1.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add property to check feature PAUTH in TEE property set

Add an entry in TEE_PROPSET_TEE_IMPLEMENTATION for a boolean
property org.trustedfirmware.optee.cpu.feat_pauth_implemented.
The property

core: Add property to check feature PAUTH in TEE property set

Add an entry in TEE_PROPSET_TEE_IMPLEMENTATION for a boolean
property org.trustedfirmware.optee.cpu.feat_pauth_implemented.
The property is set true only if CFG_TA_PAUTH is configured and
the underlying CPU supports FEAT_PAuth/FEAT_PAuth2.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32: add suspend/resume support for cortex-A5

Cortex-A5 has the same set of registers to be saved than cortex-A7. Use the
same code to save them and restore them.

Reviewed-by: Etienne Carriere <e

arm32: add suspend/resume support for cortex-A5

Cortex-A5 has the same set of registers to be saved than cortex-A7. Use the
same code to save them and restore them.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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arm64: Add support for reading register ID_AA64PFR1_EL1

Register ID_AA64PFR1_EL1 provides information about
implemented PE features in AArch64 state. Read it to determine
if BTI mechanism is support

arm64: Add support for reading register ID_AA64PFR1_EL1

Register ID_AA64PFR1_EL1 provides information about
implemented PE features in AArch64 state. Read it to determine
if BTI mechanism is supported or not.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arch/arm/include/*.h: use U() for unsigned constants

Updates with the U() macro as described in the recently updated
coding guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked

core/arch/arm/include/*.h: use U() for unsigned constants

Updates with the U() macro as described in the recently updated
coding guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arch/arm/include/*.h: se BIT() and SHIFT_U32() macros

Uses the more safe BIT() and SHIFT_U32() macros instead of direct
shifting of 1 or some other constant integer.

Acked-by: Ruchika Gupta <r

core/arch/arm/include/*.h: se BIT() and SHIFT_U32() macros

Uses the more safe BIT() and SHIFT_U32() macros instead of direct
shifting of 1 or some other constant integer.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-E

core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-EL2 SPMC" in the FFA specification.

Compile with CFG_CORE_SEL2_SPMC=y

Note that this is an experimental feature, ABIs etc may have
incompatible changes.

This depends on using the FF-A v4 patchset in the Linux kernel.

Reviewed-by: Jelle Sels <jelle.sels@arm.com>
Co-developed-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must us

Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must use CNTVCT
instead of CNTPCT while the old physical OP-TEE must continue to use
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add barrier_read_cntpct()

Adds barrier_read_cntpct() to arm.h. To be used as a helper when reading
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <eti

core: add barrier_read_cntpct()

Adds barrier_read_cntpct() to arm.h. To be used as a helper when reading
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: spci: add support to register secondary CPU entrypoints using PSCI_CPU_ON

This patch adds support to use the PSCI_CPU_ON function to register the
entry point for each OP-TEE context o

plat-vexpress: spci: add support to register secondary CPU entrypoints using PSCI_CPU_ON

This patch adds support to use the PSCI_CPU_ON function to register the
entry point for each OP-TEE context on a secondary CPU. This function is
invoked on the boot CPU during initialisation. When the physical CPU is
turned on by the Normal world, the SPMD in EL3 arranges for the entry
point to be invoked to perform OP-TEE initialisation.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
[jw: small edits + AAarch32 support]
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add support for multi-threaded MPIDR values

If the MT bit is set the affinities are shifted in the MPIDR register
so the get_core_pos_mpidr function needs to be modified accordingly.
This is n

core: Add support for multi-threaded MPIDR values

If the MT bit is set the affinities are shifted in the MPIDR register
so the get_core_pos_mpidr function needs to be modified accordingly.
This is necessary to make OP-TEE to be able to run on multi-threaded
systems. The number of threads/core can be modified by the
CFG_CORE_THREAD_SHIFT makefile parameter. The default value is the
existing single threaded mode.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm.h: add CTR_WORD_SIZE

Adds a common define for the word size used by the CTR (cache type)
register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jen

arm.h: add CTR_WORD_SIZE

Adds a common define for the word size used by the CTR (cache type)
register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm.h: add more MIDR definitions

Adds MIDR_PRIMARY_PART_NUM_MASK and MIDR_IMPLEMENTER_MASK.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wikland

core: arm.h: add more MIDR definitions

Adds MIDR_PRIMARY_PART_NUM_MASK and MIDR_IMPLEMENTER_MASK.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm.h: move midr definitions

Moves MIDR definitions from arm32.h to arm.h

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words. Therefore, we can safely remove the text from the
files that are owned by Linaro.

Generated by:
spdxify.py --linaro-only --strip-arr optee_os/

Link: [1] https://en.wikipedia.org/wiki/All_rights_reserved
Link: [2] https://reuse.software/practices/
Link: [3] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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