Lines Matching refs:U

67 #define TZC400_REG_SIZE		U(0x1000)
69 #define BUILD_CONFIG_OFF	U(0x000)
70 #define ACTION_OFF		U(0x004)
71 #define GATE_KEEPER_OFF		U(0x008)
72 #define SPECULATION_CTRL_OFF	U(0x00c)
73 #define INT_STATUS		U(0x010)
74 #define INT_CLEAR		U(0x014)
76 #define FAIL_ADDRESS_LOW_OFF	U(0x020)
77 #define FAIL_ADDRESS_HIGH_OFF	U(0x024)
78 #define FAIL_CONTROL_OFF	U(0x028)
79 #define FAIL_ID_OFF		U(0x02c)
80 #define FAIL_FILTER_OFF(idx)	(U(0x10) * (idx))
87 #define REGION_BASE_LOW_OFF	U(0x100)
88 #define REGION_BASE_HIGH_OFF	U(0x104)
89 #define REGION_TOP_LOW_OFF	U(0x108)
90 #define REGION_TOP_HIGH_OFF	U(0x10c)
91 #define REGION_ATTRIBUTES_OFF	U(0x110)
92 #define REGION_ID_ACCESS_OFF	U(0x114)
93 #define REGION_NUM_OFF(region)  (U(0x20) * (region))
96 #define PID0_OFF		U(0xfe0)
97 #define PID1_OFF		U(0xfe4)
98 #define PID2_OFF		U(0xfe8)
99 #define PID3_OFF		U(0xfec)
100 #define PID4_OFF		U(0xfd0)
101 #define PID5_OFF		U(0xfd4)
102 #define PID6_OFF		U(0xfd8)
103 #define PID7_OFF		U(0xfdc)
104 #define CID0_OFF		U(0xff0)
105 #define CID1_OFF		U(0xff4)
106 #define CID2_OFF		U(0xff8)
107 #define CID3_OFF		U(0xffc)
109 #define BUILD_CONFIG_NF_SHIFT	U(24)
110 #define BUILD_CONFIG_NF_MASK	U(0x3)
111 #define BUILD_CONFIG_AW_SHIFT	U(8)
112 #define BUILD_CONFIG_AW_MASK	U(0x3f)
113 #define BUILD_CONFIG_NR_SHIFT	U(0)
114 #define BUILD_CONFIG_NR_MASK	U(0x1f)
117 #define ACTION_RV_SHIFT		U(0)
118 #define ACTION_RV_MASK		U(0x3)
119 #define  ACTION_RV_LOWOK	U(0x0)
120 #define  ACTION_RV_LOWERR	U(0x1)
121 #define  ACTION_RV_HIGHOK	U(0x2)
122 #define  ACTION_RV_HIGHERR	U(0x3)
128 #define GATE_KEEPER_OS_SHIFT	U(16)
129 #define GATE_KEEPER_OS_MASK	U(0xf)
130 #define GATE_KEEPER_OR_SHIFT	U(0)
131 #define GATE_KEEPER_OR_MASK	U(0xf)
132 #define GATE_KEEPER_FILTER_MASK	U(0x1)
139 #define INT_STATUS_OVERLAP_SHIFT	U(16)
140 #define INT_STATUS_OVERLAP_MASK		U(0xf)
141 #define INT_STATUS_OVERRUN_SHIFT	U(8)
142 #define INT_STATUS_OVERRUN_MASK		U(0xf)
143 #define INT_STATUS_STATUS_SHIFT		U(0)
144 #define INT_STATUS_STATUS_MASK		U(0xf)
146 #define INT_CLEAR_CLEAR_SHIFT		U(0)
147 #define INT_CLEAR_CLEAR_MASK		U(0xf)
160 #define FAIL_ID_VNET_SHIFT		U(24)
161 #define FAIL_ID_VNET_MASK		U(0xf)
162 #define FAIL_ID_ID_SHIFT		U(0)
165 #define REG_ATTR_SEC_SHIFT		U(30)
166 #define REG_ATTR_F_EN_SHIFT		U(0)
167 #define REG_ATTR_F_EN_MASK		U(0xf)
172 #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT	U(16)
173 #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT	U(0)
174 #define REGION_ID_ACCESS_NSAID_ID_MASK		U(0xf)
188 #define TZC400_COMPONENT_ID	U(0xb105f00d)