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Searched refs:MEM_AREA_IO_SEC (Results 1 – 25 of 117) sorted by relevance

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/optee_os/core/arch/arm/plat-imx/
H A Dmain.c49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE);
55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000);
58 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS0_BASE,
62 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE,
66 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE,
70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE,
79 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE);
88 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
H A Dtzc380.c27 register_phys_mem(MEM_AREA_IO_SEC, TZASC2_BASE, TZASC_SIZE);
30 register_phys_mem(MEM_AREA_IO_SEC, TZASC_BASE, TZASC_SIZE);
56 addr[0] = core_mmu_get_va(TZASC_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
61 addr[1] = core_mmu_get_va(TZASC2_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
/optee_os/core/arch/arm/plat-k3/
H A Dmain.c23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TI_MAILBOX_TX_BASE,
30 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TI_MAILBOX_RX_BASE,
32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, MAILBOX_TX_START_REGION,
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, MAILBOX_RX_START_REGION,
37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SEC_PROXY_DATA_BASE,
39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SEC_PROXY_SCFG_BASE,
41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE);
/optee_os/core/arch/arm/plat-stm32mp2/
H A Dmain.c28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB1_BASE, APB1_SIZE);
29 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB2_BASE, APB2_SIZE);
30 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB3_SIZE);
31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB4_BASE, APB4_SIZE);
32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB2_BASE, AHB2_SIZE);
33 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB3_BASE, AHB3_SIZE);
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE);
35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE);
36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SAPB_BASE, SAPB_SIZE);
37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SAHB_BASE, SAHB_SIZE);
[all …]
/optee_os/core/drivers/pm/imx/
H A Dsrc.c30 register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, SRC_SIZE);
34 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_get_src_gpr_arg()
41 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_set_src_gpr_arg()
48 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_get_src_gpr_entry()
55 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_set_src_gpr_entry()
62 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_src_release_secondary_core()
74 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_src_shutdown_core()
/optee_os/core/arch/arm/plat-sunxi/
H A Dmain.c48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE);
70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE,
75 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE);
80 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_SMC_BASE, TZC400_REG_SIZE);
103 vaddr_t v = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC, in tzpc_init()
153 return (vaddr_t)phys_to_virt(SUNXI_SMC_BASE, MEM_AREA_IO_SEC, in smc_base()
/optee_os/core/arch/arm/plat-rzn1/
H A Dmain.c33 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
34 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE);
58 tza_init_reg = core_mmu_get_va(FW_STATIC_TZA_INIT, MEM_AREA_IO_SEC, in rzn1_tz_init()
60 tza_targ_reg = core_mmu_get_va(FW_STATIC_TZA_TARG, MEM_AREA_IO_SEC, in rzn1_tz_init()
84 cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
86 cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
/optee_os/core/arch/arm/plat-versal/
H A Dmain.c30 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
37 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
40 register_phys_mem(MEM_AREA_IO_SEC, PLM_RTCA, PLM_RTCA_LEN);
63 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, in platform_banner()
93 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, in plat_rpmb_key_is_ready()
/optee_os/core/arch/arm/plat-bcm/
H A Dmain.c20 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE0_BASE, BCM_DEVICE0_SIZE);
23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE1_BASE, BCM_DEVICE1_SIZE);
26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE2_BASE, BCM_DEVICE2_SIZE);
29 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE3_BASE, BCM_DEVICE3_SIZE);
32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE4_BASE, BCM_DEVICE4_SIZE);
/optee_os/core/arch/arm/plat-zynqmp/
H A Dmain.c51 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
55 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
59 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSU_BASE, CSU_SIZE);
93 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in plat_rpmb_key_is_ready()
/optee_os/core/arch/arm/plat-corstone1000/
H A Dmain.c19 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
20 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_REDIST_REG_SIZE);
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
/optee_os/core/arch/arm/plat-marvell/
H A Dmain.c61 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
64 register_phys_mem(MEM_AREA_IO_SEC, PLAT_MARVELL_FUSF_FUSE_BASE,
69 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, CORE_MMU_PGDIR_SIZE);
71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, CORE_MMU_PGDIR_SIZE);
108 MEM_AREA_IO_SEC, sizeof(hwkey->data)); in tee_otp_get_hw_unique_key()
/optee_os/core/arch/arm/plat-automotive_rd/
H A Dmain.c20 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GICR_SIZE);
/optee_os/core/drivers/
H A Dimx_snvs.c70 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_otpmk_selected()
93 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_mks_locked()
102 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in set_mks_otpmk()
115 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_otpmk_valid()
124 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, in snvs_get_security_cfg()
150 vaddr_t snvs = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, in snvs_get_ssm_mode()
201 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in imx_snvs_shutdown()
H A Dhi16xx_rng.c35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ALG_SC_BASE, ALG_SC_REG_SIZE);
36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_REG_SIZE);
42 vaddr_t alg = (vaddr_t)phys_to_virt(ALG_SC_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
44 vaddr_t rng = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
79 r = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, 1) + in hw_get_random_bytes()
H A Dzynqmp_csu_puf.c31 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_regenerate()
33 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_regenerate()
55 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_reset()
63 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_init()
H A Dzynqmp_csudma.c43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSUDMA_BASE, CSUDMA_SIZE);
47 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in csudma_clear_intr()
61 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_sync()
85 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_prepare()
100 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_unprepare()
111 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_transfer()
/optee_os/core/arch/arm/plat-rcar/
H A Dmain.c39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PRR_BASE, SMALL_PAGE_SIZE);
/optee_os/core/arch/arm/plat-hisilicon/
H A Dmain.c18 register_phys_mem(MEM_AREA_IO_SEC, BOOTSRAM_BASE, BOOTSRAM_SIZE);
21 register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
24 register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
/optee_os/core/arch/arm/plat-aspeed/
H A Dplatform_ast2700.c14 register_phys_mem(MEM_AREA_IO_SEC, UART_BASE, SMALL_PAGE_SIZE);
15 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
16 register_phys_mem(MEM_AREA_IO_SEC, GICR_BASE, GICR_SIZE);
/optee_os/core/arch/arm/plat-rzg/
H A Dmain.c14 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
15 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
16 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
/optee_os/core/arch/arm/plat-versal2/
H A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
29 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
30 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
/optee_os/core/arch/arm/plat-uniphier/
H A Dmain.c17 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
/optee_os/core/arch/arm/plat-vexpress/
H A Dmain.c36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE);
51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_REDIST_BASE, GIC_REDIST_SIZE);
238 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE);
246 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); in init_tzc400()
270 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, in release_secondary_early_hpen()
/optee_os/core/arch/arm/plat-zynq7k/
H A Dmain.c51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE);
104 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); in pl310_base()
172 MEM_AREA_IO_SEC, in write_slcr()
193 MEM_AREA_IO_SEC, in read_slcr()

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