1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2014, Allwinner Technology Co., Ltd.
4 * Copyright (c) 2018, Linaro Limited
5 * Copyright (c) 2018, Amit Singh Tomar <amittomer25@gmail.com>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright notice,
15 * this list of conditions and the following disclaimer in the documentation
16 * and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <console.h>
32 #include <io.h>
33 #include <stdint.h>
34 #include <drivers/gic.h>
35 #include <drivers/serial8250_uart.h>
36 #include <drivers/tzc380.h>
37 #include <kernel/boot.h>
38 #include <kernel/misc.h>
39 #include <kernel/panic.h>
40 #include <kernel/tz_ssvce_def.h>
41 #include <mm/core_mmu.h>
42 #include <mm/core_memprot.h>
43 #include <mm/tee_pager.h>
44 #include <platform_config.h>
45 #include <sm/optee_smc.h>
46
47 #ifdef GIC_BASE
48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
49 #endif
50
51 #ifdef CONSOLE_UART_BASE
52 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
53 CONSOLE_UART_BASE, SUNXI_UART_REG_SIZE);
54 #endif
55
56 #ifdef SUNXI_TZPC_BASE
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE);
58 #define REG_TZPC_SMTA_DECPORT0_STA_REG (0x0004)
59 #define REG_TZPC_SMTA_DECPORT0_SET_REG (0x0008)
60 #define REG_TZPC_SMTA_DECPORT0_CLR_REG (0x000C)
61 #define REG_TZPC_SMTA_DECPORT1_STA_REG (0x0010)
62 #define REG_TZPC_SMTA_DECPORT1_SET_REG (0x0014)
63 #define REG_TZPC_SMTA_DECPORT1_CLR_REG (0x0018)
64 #define REG_TZPC_SMTA_DECPORT2_STA_REG (0x001c)
65 #define REG_TZPC_SMTA_DECPORT2_SET_REG (0x0020)
66 #define REG_TZPC_SMTA_DECPORT2_CLR_REG (0x0024)
67 #endif
68
69 #ifdef SUNXI_CPUCFG_BASE
70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE,
71 SUNXI_CPUCFG_REG_SIZE);
72 #endif
73
74 #ifdef SUNXI_PRCM_BASE
75 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE);
76 #endif
77
78 #ifdef CFG_TZC380
79 vaddr_t smc_base(void);
80 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_SMC_BASE, TZC400_REG_SIZE);
81 #define SMC_MASTER_BYPASS 0x18
82 #define SMC_MASTER_BYPASS_EN_MASK 0x1
83 #endif
84
85 #ifdef SUNXI_TZPC_BASE
86 static void tzpc_init(void);
87 #endif
88
89 static struct serial8250_uart_data console_data;
90
plat_console_init(void)91 void plat_console_init(void)
92 {
93 serial8250_uart_init(&console_data,
94 CONSOLE_UART_BASE,
95 CONSOLE_UART_CLK_IN_HZ,
96 CONSOLE_BAUDRATE);
97 register_serial_console(&console_data.chip);
98 }
99
100 #ifdef SUNXI_TZPC_BASE
tzpc_init(void)101 static void tzpc_init(void)
102 {
103 vaddr_t v = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC,
104 SUNXI_TZPC_REG_SIZE);
105
106 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG));
107 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG));
108 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG));
109
110 /* Allow all peripherals for normal world */
111 io_write32(v + REG_TZPC_SMTA_DECPORT0_SET_REG, 0xbe);
112 io_write32(v + REG_TZPC_SMTA_DECPORT1_SET_REG, 0xff);
113 io_write32(v + REG_TZPC_SMTA_DECPORT2_SET_REG, 0x7f);
114
115 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG));
116 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG));
117 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG));
118 }
119 #else
tzpc_init(void)120 static inline void tzpc_init(void)
121 {
122 }
123 #endif /* SUNXI_TZPC_BASE */
124
125 #ifndef CFG_WITH_ARM_TRUSTED_FW
boot_primary_init_intc(void)126 void boot_primary_init_intc(void)
127 {
128 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
129 }
130
boot_secondary_init_intc(void)131 void boot_secondary_init_intc(void)
132 {
133 gic_init_per_cpu();
134 }
135 #endif
136
137 #ifdef ARM32
plat_primary_init_early(void)138 void plat_primary_init_early(void)
139 {
140 assert(!cpu_mmu_enabled());
141
142 tzpc_init();
143 }
144 #endif
145
146 /*
147 * Allwinner's A64 has TZC380 like controller called SMC that can
148 * be programmed to protect parts of DRAM from non-secure world.
149 */
150 #ifdef CFG_TZC380
smc_base(void)151 vaddr_t smc_base(void)
152 {
153 return (vaddr_t)phys_to_virt(SUNXI_SMC_BASE, MEM_AREA_IO_SEC,
154 TZC400_REG_SIZE);
155 }
156
smc_init(void)157 static TEE_Result smc_init(void)
158 {
159 vaddr_t base = smc_base();
160
161 if (!base) {
162 EMSG("smc not mapped");
163 panic();
164 }
165
166 tzc_init(base);
167 tzc_configure_region(0, 0x0, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_1G) |
168 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
169 tzc_configure_region(1, 0x0, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) |
170 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW);
171
172 /* SoC specific bits */
173 io_clrbits32(base + SMC_MASTER_BYPASS, SMC_MASTER_BYPASS_EN_MASK);
174
175 return TEE_SUCCESS;
176 }
177
178 driver_init(smc_init);
179 #endif /* CFG_TZC380 */
180