xref: /optee_os/core/arch/arm/plat-hisilicon/main.c (revision 55ab8f06a831946a49717446cd2e4495a2b5d659)
1b7667020SZeng Tao // SPDX-License-Identifier: BSD-2-Clause
2b7667020SZeng Tao /*
3b7667020SZeng Tao  * Copyright (c) 2019, HiSilicon Technologies Co., Ltd.
4b7667020SZeng Tao  */
5b7667020SZeng Tao 
6b7667020SZeng Tao #include <console.h>
7b7667020SZeng Tao #include <drivers/gic.h>
8b7667020SZeng Tao #include <drivers/pl011.h>
9b7667020SZeng Tao #include <kernel/panic.h>
10b7667020SZeng Tao #include <mm/tee_pager.h>
11b7667020SZeng Tao #include <mm/core_memprot.h>
12b7667020SZeng Tao #include <platform_config.h>
13b7667020SZeng Tao #include <stdint.h>
14b7667020SZeng Tao 
15b7667020SZeng Tao static struct pl011_data console_data;
16b7667020SZeng Tao register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
17b7667020SZeng Tao #ifdef BOOTSRAM_BASE
18b7667020SZeng Tao register_phys_mem(MEM_AREA_IO_SEC, BOOTSRAM_BASE, BOOTSRAM_SIZE);
19b7667020SZeng Tao #endif
20b7667020SZeng Tao #ifdef CPU_CRG_BASE
21b7667020SZeng Tao register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
22b7667020SZeng Tao #endif
23b7667020SZeng Tao #ifdef SYS_CTRL_BASE
24b7667020SZeng Tao register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
25b7667020SZeng Tao #endif
26b7667020SZeng Tao 
plat_console_init(void)27*55ab8f06SAlvin Chang void plat_console_init(void)
28b7667020SZeng Tao {
29b7667020SZeng Tao 	pl011_init(&console_data, CONSOLE_UART_BASE,
30b7667020SZeng Tao 		CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
31b7667020SZeng Tao 	register_serial_console(&console_data.chip);
32b7667020SZeng Tao }
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