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Searched refs:GICC_OFFSET (Results 1 – 25 of 38) sorted by relevance

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/optee_os/core/arch/arm/plat-ls/
H A Dplatform_config.h45 #define GICC_OFFSET 0x2000 macro
68 #define GICC_OFFSET 0x20000 macro
78 #define GICC_OFFSET 0x0 macro
88 #define GICC_OFFSET 0x0 macro
98 #define GICC_OFFSET 0x0 macro
108 #define GICC_OFFSET 0x0 macro
118 #define GICC_OFFSET 0x0 macro
/optee_os/core/arch/arm/plat-mediatek/
H A Dplatform_config.h23 #define GICC_OFFSET 0x2000 macro
41 #define GICC_OFFSET 0x400000 macro
55 #define GICC_OFFSET 0x10000 macro
69 #define GICC_OFFSET 0x400000 macro
83 #define GICC_OFFSET 0x400000 macro
97 #define GICC_OFFSET 0x400000 macro
111 #define GICC_OFFSET 0x400000 macro
H A Dmain.c27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET,
32 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
/optee_os/core/arch/arm/plat-vexpress/
H A Dplatform_config.h109 #define GICC_OFFSET 0x0 macro
127 #define GICC_OFFSET 0x1f000 macro
139 #define GICC_OFFSET 0x10000 macro
144 #define GICC_OFFSET 0x10000 macro
152 #define GICC_OFFSET 0x10000 macro
160 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-ti/
H A Dplatform_config.h40 #define GICC_OFFSET 0x2000 macro
44 #define GICC_BASE (SCU_BASE + GICC_OFFSET)
76 #define GICC_OFFSET 0x0100 macro
81 #define GICC_BASE (SCU_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-marvell/
H A Dplatform_config.h69 #define GICC_OFFSET 0x10000 macro
73 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
99 #define GICC_OFFSET (0x80000) macro
104 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-rzn1/
H A Dplatform_config.h19 #define GICC_OFFSET 0x2000 macro
21 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-nuvoton/
H A Dplatform_config.h21 #define GICC_OFFSET 0x2000 macro
23 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-totalcompute/
H A Dplatform_config.h20 #define GICC_OFFSET 0x0 macro
43 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
H A Dmain.c31 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICC_OFFSET); in boot_primary_init_intc()
/optee_os/core/arch/arm/plat-k3/
H A Dplatform_config.h26 #define GICC_OFFSET 0x100000 macro
31 #define GICC_OFFSET 0x80000 macro
72 #define GICC_BASE (SCU_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-imx/registers/
H A Dimx6.h89 #define GICC_OFFSET 0x2000 macro
95 #define GICC_OFFSET 0x100 macro
100 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
H A Dimx7ulp.h13 #define GICC_OFFSET 0x2000 macro
/optee_os/core/arch/arm/plat-corstone1000/
H A Dplatform_config.h34 #define GICC_OFFSET 0x2F000 macro
40 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-zynq7k/
H A Dplatform_config.h39 #define GICC_OFFSET 0x100 macro
41 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
/optee_os/core/arch/arm/plat-aspeed/
H A Dplatform_ast2600.c48 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET, GIC_CPU_REG_SIZE);
65 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
H A Dplatform_config.h16 #define GICC_OFFSET 0x2000 macro
/optee_os/core/arch/arm/plat-amlogic/
H A Dplatform_config.h15 #define GICC_OFFSET 0x2000 macro
/optee_os/core/arch/arm/plat-sunxi/
H A Dplatform_config.h47 #define GICC_OFFSET 0x2000 macro
/optee_os/core/arch/arm/plat-uniphier/
H A Dplatform_config.h18 #define GICC_OFFSET 0x80000 macro
H A Dmain.c40 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
/optee_os/core/arch/arm/plat-sprd/
H A Dmain.c50 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in boot_primary_init_intc()
H A Dplatform_config.h60 #define GICC_OFFSET 0x2000 macro
/optee_os/core/arch/arm/plat-versal/
H A Dplatform_config.h45 #define GICC_OFFSET 0x40000 macro
/optee_os/core/arch/arm/plat-zynqmp/
H A Dplatform_config.h74 #define GICC_OFFSET 0x10000 macro

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