1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2021, Aspeed Technology Inc.
4 */
5
6 #include <console.h>
7 #include <drivers/gic.h>
8 #include <drivers/serial8250_uart.h>
9 #include <mm/core_memprot.h>
10 #include <platform_config.h>
11 #include <stdint.h>
12 #include <io.h>
13 #include <kernel/boot.h>
14 #include <kernel/panic.h>
15
16 enum TZM_PERM {
17 TZM_PERM_VGA_CURSOR_RD,
18 TZM_PERM_VGA_CRT_RD,
19 TZM_PERM_SOC_DISPLAY_RD,
20 TZM_PERM_PCIE_BUS1_RW,
21 TZM_PERM_VIDEO_HIGH_WR,
22 TZM_PERM_CPU_RW,
23 TZM_PERM_SLI_RW,
24 TZM_PERM_PCIE_BUS2_RW,
25 TZM_PERM_USB20_HUB_EHCI1_DMA_RW,
26 TZM_PERM_USB20_DEV_EHCI2_DMA_RW,
27 TZM_PERM_USB11_UCHI_HOST_RW,
28 TZM_PERM_AHB_RW,
29 TZM_PERM_CM3_DATA_RW,
30 TZM_PERM_CM3_INSN_RW,
31 TZM_PERM_MAC0_DMA_RW,
32 TZM_PERM_MAC1_DMA_RW,
33 TZM_PERM_SDIO_DMA_RW,
34 TZM_PERM_PILOT_RW,
35 TZM_PERM_XDMA1_RW,
36 TZM_PERM_MCTP1_RW,
37 TZM_PERM_VIDEO_FLAG_RW,
38 TZM_PERM_VIDEO_LOW_WR,
39 TZM_PERM_2D_DATA_RW,
40 TZM_PERM_ENCRYPT_RW,
41 TZM_PERM_MCTP2_RW,
42 TZM_PERM_XDMA2_RW,
43 TZM_PERM_ECC_RSA_RW,
44 };
45
46 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, SMALL_PAGE_SIZE);
47 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET, GIC_DIST_REG_SIZE);
48 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET, GIC_CPU_REG_SIZE);
49 register_phys_mem(MEM_AREA_IO_SEC, AHBC_BASE, SMALL_PAGE_SIZE);
50 register_phys_mem(MEM_AREA_IO_NSEC, SCU_BASE, SMALL_PAGE_SIZE);
51
52 #define AHBC_REG_WR_PROT 0x204
53 #define AHBC_TZP_ACCESS1 0x280
54 #define AHBC_TZP_HACE BIT(20)
55 #define AHBC_TZM_ST(i) (0x300 + ((i) * 0x10))
56 #define AHBC_TZM_ED(i) (0x304 + ((i) * 0x10))
57 #define AHBC_TZM_PERM(i) (0x308 + ((i) * 0x10))
58
59 register_ddr(CFG_DRAM_BASE, CFG_DRAM_SIZE);
60
61 static struct serial8250_uart_data console_data;
62
boot_primary_init_intc(void)63 void boot_primary_init_intc(void)
64 {
65 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
66 }
67
boot_secondary_init_intc(void)68 void boot_secondary_init_intc(void)
69 {
70 gic_init_per_cpu();
71 }
72
plat_console_init(void)73 void plat_console_init(void)
74 {
75 serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
76 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
77 register_serial_console(&console_data.chip);
78 }
79
plat_primary_init_early(void)80 void plat_primary_init_early(void)
81 {
82 vaddr_t ahbc_virt = 0;
83 uint32_t tzm_perm = 0;
84
85 ahbc_virt = core_mmu_get_va(AHBC_BASE,
86 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE);
87 if (!ahbc_virt)
88 panic();
89
90 tzm_perm = BIT(TZM_PERM_CPU_RW);
91 if (IS_ENABLED(CFG_ASPEED_CRYPTO_DRIVER)) {
92 tzm_perm |= BIT(TZM_PERM_ENCRYPT_RW);
93 io_write32(ahbc_virt + AHBC_TZP_ACCESS1, AHBC_TZP_HACE);
94 }
95
96 io_write32(ahbc_virt + AHBC_TZM_PERM(0), tzm_perm);
97 io_write32(ahbc_virt + AHBC_TZM_ED(0),
98 CFG_TZDRAM_START + CFG_TZDRAM_SIZE - 1);
99 io_write32(ahbc_virt + AHBC_TZM_ST(0),
100 CFG_TZDRAM_START | BIT(0));
101 io_write32(ahbc_virt + AHBC_REG_WR_PROT, BIT(16));
102 }
103