1c3d61baaSClement Faure /* SPDX-License-Identifier: BSD-2-Clause */ 2c3d61baaSClement Faure /* 3c3d61baaSClement Faure * Copyright 2017-2019 NXP 4c3d61baaSClement Faure */ 5c3d61baaSClement Faure 6c3d61baaSClement Faure #ifndef __IMX7ULP_H__ 7c3d61baaSClement Faure #define __IMX7ULP_H__ 8c3d61baaSClement Faure 90f68a8c3SClement Faure #include <registers/imx7ulp-crm.h> 100f68a8c3SClement Faure 11c3d61baaSClement Faure #define GIC_BASE 0x40020000 12c3d61baaSClement Faure #define GIC_SIZE 0x8000 13c3d61baaSClement Faure #define GICC_OFFSET 0x2000 14c3d61baaSClement Faure #define GICD_OFFSET 0x1000 15c3d61baaSClement Faure 16c3d61baaSClement Faure #define AIPS0_BASE 0x40000000 17c3d61baaSClement Faure #define AIPS0_SIZE 0x800000 18c3d61baaSClement Faure #define AIPS1_BASE 0x40800000 19c3d61baaSClement Faure #define AIPS1_SIZE 0x800000 20c3d61baaSClement Faure #define M4_AIPS_BASE 0x41000000 21c3d61baaSClement Faure #define M4_AIPS_SIZE 0x100000 22c3d61baaSClement Faure #define M4_AIPS0_BASE 0x41000000 23c3d61baaSClement Faure #define M4_AIPS0_SIZE 0x80000 24c3d61baaSClement Faure #define M4_AIPS1_BASE 0x41080000 25c3d61baaSClement Faure #define M4_AIPS1_SIZE 0x80000 26c3d61baaSClement Faure 27c3d61baaSClement Faure #define GPIOC_BASE 0x400f0000 28c3d61baaSClement Faure #define GPIOD_BASE 0x400f0040 29c3d61baaSClement Faure #define GPIOE_BASE 0x400f0080 30c3d61baaSClement Faure #define GPIOF_BASE 0x400f00c0 31c3d61baaSClement Faure #define TPM5_BASE 0x40260000 32c54ad22aSClement Faure #define WDOG_BASE 0x403d0000 33c54ad22aSClement Faure #define WDOG_SIZE 0x10 34c3d61baaSClement Faure #define SCG1_BASE 0x403e0000 35c3d61baaSClement Faure #define PCC2_BASE 0x403f0000 36c3d61baaSClement Faure #define PMC1_BASE 0x40400000 37c3d61baaSClement Faure #define SMC1_BASE 0x40410000 38c3d61baaSClement Faure #define MMDC_BASE 0x40ab0000 39c3d61baaSClement Faure #define IOMUXC1_BASE 0x40ac0000 40c3d61baaSClement Faure #define MMDC_IO_BASE 0x40ad0000 41c3d61baaSClement Faure #define PCC3_BASE 0x40b30000 42e4ca953cSClement Faure #define OCOTP_BASE 0x410A6000 43e4ca953cSClement Faure #define OCOTP_SIZE 0x4000 44c3d61baaSClement Faure #define PMC0_BASE 0x410a1000 45c3d61baaSClement Faure #define SIM_BASE 0x410a3000 460a8e42ddSClement Faure #define OCOTP_BASE 0x410A6000 470a8e42ddSClement Faure #define OCOTP_SIZE 0x4000 48c3d61baaSClement Faure 49c3d61baaSClement Faure #define CAAM_BASE 0x40240000 50*2866fd96SClement Faure #define CAAM_SIZE 0x10000 51c3d61baaSClement Faure #define UART4_BASE 0x402d0000 52c3d61baaSClement Faure #define UART5_BASE 0x402e0000 53c3d61baaSClement Faure #define UART6_BASE 0x40a60000 54c3d61baaSClement Faure #define UART7_BASE 0x40a70000 55c3d61baaSClement Faure 56c3d61baaSClement Faure #define IRAM_BASE 0x1FFFC000 57c3d61baaSClement Faure #define IRAM_SIZE 0x4000 58c3d61baaSClement Faure 59c3d61baaSClement Faure #define LP_OCRAM_START IRAM_BASE 60c3d61baaSClement Faure 61c3d61baaSClement Faure #endif /* __IMX7ULP_H__ */ 62