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Searched refs:DRAM0_SIZE (Results 1 – 25 of 33) sorted by relevance

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/optee_os/core/arch/arm/plat-poplar/
H A Dplatform_config.h101 #define DRAM0_SIZE 0x80000000 macro
103 #define DRAM0_SIZE 0x40000000 macro
109 #define DRAM0_SIZE_NSEC (DRAM0_SIZE - DRAM0_BASE_NSEC)
/optee_os/core/arch/arm/plat-automotive_rd/
H A Dplatform_config.h19 #define DRAM0_SIZE SIZE_2G macro
43 #define DRAM0_SIZE SIZE_2G macro
H A Dmain.c17 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-vexpress/
H A Dplatform_config.h101 #define DRAM0_SIZE 0x7f000000 macro
122 #define DRAM0_SIZE 0x7F000000 macro
/optee_os/core/arch/arm/plat-rpi5/
H A Dplatform_config.h20 #define DRAM0_SIZE 0x200000000 macro
/optee_os/core/arch/arm/plat-rpi3/
H A Dplatform_config.h69 #define DRAM0_SIZE 0x40000000 macro
/optee_os/core/arch/arm/plat-synquacer/
H A Dplatform_config.h30 #define DRAM0_SIZE 0x80000000 macro
/optee_os/core/arch/arm/plat-d02/
H A Dplatform_config.h68 #define DRAM0_SIZE 0x50000000 macro
/optee_os/core/arch/arm/plat-nuvoton/
H A Dplatform_config.h15 #define DRAM0_SIZE 0x40000000 /* 1G DDR */ macro
/optee_os/core/arch/arm/plat-uniphier/
H A Dplatform_config.h50 #define DRAM0_SIZE (CFG_DRAM0_SIZE - CFG_DRAM0_RSV_SIZE) macro
H A Dmain.c30 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-qcom/
H A Dplatform_config.h17 #define DRAM0_SIZE UL(0x80000000) macro
H A Dmain.c24 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-totalcompute/
H A Dplatform_config.h29 #define DRAM0_SIZE 0x7d000000 macro
H A Dmain.c25 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-versal2/
H A Dmain.c32 register_ddr(DRAM0_BASE, DRAM0_SIZE);
H A Dplatform_config.h45 #define DRAM0_SIZE 0x80000000 macro
/optee_os/core/arch/arm/plat-corstone1000/
H A Dplatform_config.h21 #define DRAM0_SIZE CFG_DDR_SIZE macro
H A Dmain.c17 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-versal/
H A Dplatform_config.h34 #define DRAM0_SIZE 0x80000000 macro
/optee_os/core/arch/arm/plat-sprd/
H A Dplatform_config.h52 #define DRAM0_SIZE 0x20000000 macro
/optee_os/core/arch/arm/plat-telechips/tcc805x/
H A Dplatform_config.h46 #define DRAM0_SIZE U(0xA0000000) /* 2.5 GiB */ macro
/optee_os/core/arch/arm/plat-telechips/
H A Dmain.c21 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-mediatek/
H A Dplatform_config.h36 #define DRAM0_SIZE 0x80000000 macro
/optee_os/core/arch/arm/plat-hikey/
H A Dplatform_config.h109 #define DRAM0_SIZE (CFG_TZDRAM_START - DRAM0_BASE) macro

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