xref: /optee_os/core/arch/arm/plat-altera/main.c (revision c12c2c9b50a1087734011a3330b04d0601c104ea)
1*c12c2c9bSJit Loon Lim // SPDX-License-Identifier: BSD-2-Clause
2*c12c2c9bSJit Loon Lim /*
3*c12c2c9bSJit Loon Lim  * Copyright (c) 2026, Altera Corporation.
4*c12c2c9bSJit Loon Lim  */
5*c12c2c9bSJit Loon Lim 
6*c12c2c9bSJit Loon Lim #include <console.h>
7*c12c2c9bSJit Loon Lim #include <drivers/serial8250_uart.h>
8*c12c2c9bSJit Loon Lim #include <kernel/boot.h>
9*c12c2c9bSJit Loon Lim #include <mm/core_memprot.h>
10*c12c2c9bSJit Loon Lim #include "platform_config.h"
11*c12c2c9bSJit Loon Lim 
12*c12c2c9bSJit Loon Lim static struct serial8250_uart_data uart_console;
13*c12c2c9bSJit Loon Lim 
plat_console_init(void)14*c12c2c9bSJit Loon Lim void plat_console_init(void)
15*c12c2c9bSJit Loon Lim {
16*c12c2c9bSJit Loon Lim 	serial8250_uart_init(&uart_console,
17*c12c2c9bSJit Loon Lim 			     CONSOLE_UART_BASE,
18*c12c2c9bSJit Loon Lim 			     CONSOLE_UART_CLK_IN_HZ,
19*c12c2c9bSJit Loon Lim 			     CONSOLE_BAUDRATE);
20*c12c2c9bSJit Loon Lim 	register_serial_console(&uart_console.chip);
21*c12c2c9bSJit Loon Lim }
22*c12c2c9bSJit Loon Lim 
23*c12c2c9bSJit Loon Lim /* Map UART registers as I/O memory */
24*c12c2c9bSJit Loon Lim register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
25*c12c2c9bSJit Loon Lim 			SERIAL8250_UART_REG_SIZE);
26*c12c2c9bSJit Loon Lim 
27*c12c2c9bSJit Loon Lim /* Register main DDR for dynamic shared memory */
28*c12c2c9bSJit Loon Lim register_ddr(DRAM0_BASE, DRAM0_SIZE);
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