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Searched refs:regbase (Results 1 – 25 of 94) sorted by relevance

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/OK3568_Linux_fs/kernel/include/video/
H A Dvga.h218 static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port) in vga_mm_r() argument
220 return readb (regbase + port); in vga_mm_r()
223 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) in vga_mm_w() argument
225 writeb (val, regbase + port); in vga_mm_w()
228 static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port, in vga_mm_w_fast() argument
231 writew (VGA_OUT16VAL (val, reg), regbase + port); in vga_mm_w_fast()
234 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) in vga_r() argument
236 if (regbase) in vga_r()
237 return vga_mm_r (regbase, port); in vga_r()
242 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) in vga_w() argument
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/OK3568_Linux_fs/kernel/arch/mips/netlogic/xlp/
H A Dahci-init-xlp2.c169 static void sata_clear_glue_reg(u64 regbase, u32 off, u32 bit) in sata_clear_glue_reg() argument
173 reg_val = nlm_read_sata_reg(regbase, off); in sata_clear_glue_reg()
174 nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); in sata_clear_glue_reg()
177 static void sata_set_glue_reg(u64 regbase, u32 off, u32 bit) in sata_set_glue_reg() argument
181 reg_val = nlm_read_sata_reg(regbase, off); in sata_set_glue_reg()
182 nlm_write_sata_reg(regbase, off, (reg_val | bit)); in sata_set_glue_reg()
185 static void write_phy_reg(u64 regbase, u32 addr, u32 physel, u8 data) in write_phy_reg() argument
187 nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, in write_phy_reg()
192 static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel) in read_phy_reg() argument
196 nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, in read_phy_reg()
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H A Dahci-init.c95 static void sata_clear_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) in sata_clear_glue_reg() argument
99 reg_val = nlm_read_sata_reg(regbase, off); in sata_clear_glue_reg()
100 nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); in sata_clear_glue_reg()
103 static void sata_set_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) in sata_set_glue_reg() argument
107 reg_val = nlm_read_sata_reg(regbase, off); in sata_set_glue_reg()
108 nlm_write_sata_reg(regbase, off, (reg_val | bit)); in sata_set_glue_reg()
114 uint64_t regbase; in nlm_sata_firmware_init() local
118 regbase = nlm_get_sata_regbase(node); in nlm_sata_firmware_init()
121 sata_clear_glue_reg(regbase, SATA_CTL, SATA_RST_N); in nlm_sata_firmware_init()
123 sata_clear_glue_reg(regbase, SATA_CTL, in nlm_sata_firmware_init()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dwmt_ge_rops.c39 static void __iomem *regbase; variable
60 (p->var.bits_per_pixel == 8 ? 0 : 1), regbase + GE_DEPTH_OFF); in wmt_ge_fillrect()
61 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); in wmt_ge_fillrect()
62 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); in wmt_ge_fillrect()
63 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); in wmt_ge_fillrect()
64 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); in wmt_ge_fillrect()
65 writel(rect->dx, regbase + GE_DESTAREAX_OFF); in wmt_ge_fillrect()
66 writel(rect->dy, regbase + GE_DESTAREAY_OFF); in wmt_ge_fillrect()
67 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); in wmt_ge_fillrect()
68 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); in wmt_ge_fillrect()
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H A Dcirrusfb.c355 u8 __iomem *regbase; member
395 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
396 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
401 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
410 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
412 caddr_t regbase,
451 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
637 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
643 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
647 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); in cirrusfb_set_mclk_as_source()
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H A Dwm8505fb.c38 void __iomem *regbase; member
51 writel(0, fbi->regbase + i); in wm8505fb_init_hw()
54 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR); in wm8505fb_init_hw()
55 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1); in wm8505fb_init_hw()
62 writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE); in wm8505fb_init_hw()
63 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1); in wm8505fb_init_hw()
66 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES); in wm8505fb_init_hw()
67 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL); in wm8505fb_init_hw()
70 writel(0xf, fbi->regbase + WMT_GOVR_FHI); in wm8505fb_init_hw()
71 writel(4, fbi->regbase + WMT_GOVR_DVO_SET); in wm8505fb_init_hw()
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H A Dvt8500lcdfb.c112 control0 = readl(fbi->regbase) & ~0xf; in vt8500lcd_set_par()
113 writel(0, fbi->regbase); in vt8500lcd_set_par()
114 while (readl(fbi->regbase + 0x38) & 0x10) in vt8500lcd_set_par()
119 | (info->var.right_margin & 0xff), fbi->regbase + 0x4); in vt8500lcd_set_par()
123 | (info->var.lower_margin & 0xff), fbi->regbase + 0x8); in vt8500lcd_set_par()
125 | ((info->var.xres - 1) & 0x400), fbi->regbase + 0x10); in vt8500lcd_set_par()
126 writel(0x80000000, fbi->regbase + 0x20); in vt8500lcd_set_par()
127 writel(control0 | (reg_bpp << 1) | 0x100, fbi->regbase); in vt8500lcd_set_par()
186 writel(0xffffffff ^ (1 << 3), fbi->regbase + 0x3c); in vt8500lcd_ioctl()
188 readl(fbi->regbase + 0x38) & (1 << 3), HZ / 10); in vt8500lcd_ioctl()
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/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Dcomedi_8255.c37 unsigned long regbase; member
39 unsigned long regbase);
43 int dir, int port, int data, unsigned long regbase) in subdev_8255_io() argument
46 outb(data, dev->iobase + regbase + port); in subdev_8255_io()
49 return inb(dev->iobase + regbase + port); in subdev_8255_io()
53 int dir, int port, int data, unsigned long regbase) in subdev_8255_mmio() argument
56 writeb(data, dev->mmio + regbase + port); in subdev_8255_mmio()
59 return readb(dev->mmio + regbase + port); in subdev_8255_mmio()
68 unsigned long regbase = spriv->regbase; in subdev_8255_insn() local
76 s->state & 0xff, regbase); in subdev_8255_insn()
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/OK3568_Linux_fs/u-boot/drivers/irq/
H A Dirq-gpio.c51 static void gpio_bit_op(void __iomem *regbase, unsigned int offset, in gpio_bit_op() argument
54 u32 val = readl(regbase + offset); in gpio_bit_op()
61 writel(val, regbase + offset); in gpio_bit_op()
64 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit) in gpio_bit_rd() argument
66 return readl(regbase + offset) & bit ? 1 : 0; in gpio_bit_rd()
69 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit) in gpio_irq_unmask() argument
71 gpio_bit_op(regbase, GPIO_INTEN, bit, 1); in gpio_irq_unmask()
74 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit) in gpio_irq_mask() argument
76 gpio_bit_op(regbase, GPIO_INTEN, bit, 0); in gpio_irq_mask()
79 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit) in gpio_irq_ack() argument
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H A Dirq-gpio-v2.c54 static void gpio_bit_op(void __iomem *regbase, unsigned int offset, in gpio_bit_op() argument
63 writel(val, regbase + offset); in gpio_bit_op()
66 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit) in gpio_bit_rd() argument
71 return readl(regbase + offset) & bit ? 1 : 0; in gpio_bit_rd()
74 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit) in gpio_irq_unmask() argument
76 gpio_bit_op(regbase, GPIO_INTEN, bit, 1); in gpio_irq_unmask()
79 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit) in gpio_irq_mask() argument
81 gpio_bit_op(regbase, GPIO_INTEN, bit, 0); in gpio_irq_mask()
84 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit) in gpio_irq_ack() argument
86 gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1); in gpio_irq_ack()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/core/
H A Dsvgalib.c23 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wcrt_multi() argument
28 regval = vga_rcrt(regbase, regset->regnum); in svga_wcrt_multi()
37 vga_wcrt(regbase, regset->regnum, regval); in svga_wcrt_multi()
43 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wseq_multi() argument
48 regval = vga_rseq(regbase, regset->regnum); in svga_wseq_multi()
57 vga_wseq(regbase, regset->regnum, regval); in svga_wseq_multi()
78 void svga_set_default_gfx_regs(void __iomem *regbase) in svga_set_default_gfx_regs() argument
81 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00); in svga_set_default_gfx_regs()
82 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00); in svga_set_default_gfx_regs()
83 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00); in svga_set_default_gfx_regs()
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/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Duniphier-sd.c128 void __iomem *regbase; member
160 u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2); in uniphier_sd_check_error()
198 while (!(readl(priv->regbase + reg) & flag)) { in uniphier_sd_wait_for_irq()
230 writel(0, priv->regbase + UNIPHIER_SD_INFO2); in uniphier_sd_pio_read_one_block()
234 *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF); in uniphier_sd_pio_read_one_block()
237 put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF), in uniphier_sd_pio_read_one_block()
256 writel(0, priv->regbase + UNIPHIER_SD_INFO2); in uniphier_sd_pio_write_one_block()
260 writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF); in uniphier_sd_pio_write_one_block()
264 priv->regbase + UNIPHIER_SD_BUF); in uniphier_sd_pio_write_one_block()
295 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1); in uniphier_sd_dma_start()
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/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-sh.c97 void __iomem *regbase; member
114 tmp = readb(rtc->regbase + RCR1); in __sh_rtc_interrupt()
117 writeb(tmp, rtc->regbase + RCR1); in __sh_rtc_interrupt()
130 tmp = readb(rtc->regbase + RCR1); in __sh_rtc_alarm()
133 writeb(tmp, rtc->regbase + RCR1); in __sh_rtc_alarm()
145 tmp = readb(rtc->regbase + RCR2); in __sh_rtc_periodic()
148 writeb(tmp, rtc->regbase + RCR2); in __sh_rtc_periodic()
222 tmp = readb(rtc->regbase + RCR1); in sh_rtc_setaie()
229 writeb(tmp, rtc->regbase + RCR1); in sh_rtc_setaie()
239 tmp = readb(rtc->regbase + RCR1); in sh_rtc_proc()
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H A Drtc-vt8500.c73 void __iomem *regbase; member
88 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
89 writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
106 date = readl(vt8500_rtc->regbase + VT8500_RTC_DR); in vt8500_rtc_read_time()
107 time = readl(vt8500_rtc->regbase + VT8500_RTC_TR); in vt8500_rtc_read_time()
129 vt8500_rtc->regbase + VT8500_RTC_DS); in vt8500_rtc_set_time()
134 vt8500_rtc->regbase + VT8500_RTC_TS); in vt8500_rtc_set_time()
144 alarm = readl(vt8500_rtc->regbase + VT8500_RTC_AS); in vt8500_rtc_read_alarm()
145 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_read_alarm()
167 vt8500_rtc->regbase + VT8500_RTC_AS); in vt8500_rtc_set_alarm()
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/OK3568_Linux_fs/kernel/include/linux/
H A Dsvga.h71 static inline void svga_wattr(void __iomem *regbase, u8 index, u8 data) in svga_wattr() argument
73 vga_r(regbase, VGA_IS1_RC); in svga_wattr()
74 vga_w(regbase, VGA_ATT_IW, index); in svga_wattr()
75 vga_w(regbase, VGA_ATT_W, data); in svga_wattr()
80 static inline void svga_wseq_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) in svga_wseq_mask() argument
82 vga_wseq(regbase, index, (data & mask) | (vga_rseq(regbase, index) & ~mask)); in svga_wseq_mask()
87 static inline void svga_wcrt_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) in svga_wcrt_mask() argument
89 vga_wcrt(regbase, index, (data & mask) | (vga_rcrt(regbase, index) & ~mask)); in svga_wcrt_mask()
100 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value);
101 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value);
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-vt8500.c41 static void __iomem *regbase; variable
46 writel(3, regbase + TIMER_CTRL_VAL); in vt8500_timer_read()
47 while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) in vt8500_timer_read()
50 return readl(regbase + TIMER_COUNT_VAL); in vt8500_timer_read()
66 while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) in vt8500_timer_set_next_event()
69 writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); in vt8500_timer_set_next_event()
74 writel(1, regbase + TIMER_IER_VAL); in vt8500_timer_set_next_event()
81 writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); in vt8500_shutdown()
82 writel(0, regbase + TIMER_IER_VAL); in vt8500_shutdown()
98 writel(0xf, regbase + TIMER_STATUS_VAL); in vt8500_timer_interrupt()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ata/
H A Dsata_mv.c255 u32 regbase; member
288 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA); in mv_stop_edma_engine()
292 u32 reg = in_le32(priv->regbase + EDMA_CMD); in mv_stop_edma_engine()
309 tmp = in_le32(priv->regbase + SIR_SSTATUS); in mv_start_edma_engine()
315 tmp = in_le32(priv->regbase + PIO_CMD_STATUS); in mv_start_edma_engine()
322 out_le32(priv->regbase + EDMA_IECR, 0x0); in mv_start_edma_engine()
329 tmp = in_le32(priv->regbase + EDMA_CFG); in mv_start_edma_engine()
332 out_le32(priv->regbase + EDMA_CFG, tmp); in mv_start_edma_engine()
334 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0); in mv_start_edma_engine()
337 out_le32(priv->regbase + SIR_FIS_CFG, 0x0); in mv_start_edma_engine()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/rb532/
H A Dgpio.c42 void __iomem *regbase; member
92 return !!rb532_get_bit(offset, gpch->regbase + GPIOD); in rb532_gpio_get()
104 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_set()
117 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC); in rb532_gpio_direction_input()
119 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); in rb532_gpio_direction_input()
134 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC); in rb532_gpio_direction_output()
137 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_direction_output()
139 rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); in rb532_gpio_direction_output()
168 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); in rb532_gpio_set_ilevel()
177 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); in rb532_gpio_set_istat()
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/OK3568_Linux_fs/u-boot/drivers/spi/
H A Dcadence_qspi_apb.c380 cadence_qspi_apb_controller_disable(plat->regbase); in cadence_qspi_apb_controller_init()
383 reg = readl(plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
389 writel(reg, plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
392 writel(0, plat->regbase + CQSPI_REG_REMAP); in cadence_qspi_apb_controller_init()
395 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION); in cadence_qspi_apb_controller_init()
398 writel(0, plat->regbase + CQSPI_REG_IRQMASK); in cadence_qspi_apb_controller_init()
400 cadence_qspi_apb_controller_enable(plat->regbase); in cadence_qspi_apb_controller_init()
556 plat->regbase + CQSPI_REG_INDIRECTTRIGGER); in cadence_qspi_apb_indirect_read_setup()
567 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); in cadence_qspi_apb_indirect_read_setup()
577 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); in cadence_qspi_apb_indirect_read_setup()
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H A Drockchip_sfc.c179 void __iomem *regbase; member
199 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); in rockchip_sfc_reset()
201 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, in rockchip_sfc_reset()
208 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); in rockchip_sfc_reset()
215 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); in rockchip_sfc_get_version()
251 writel(val, sfc->regbase + SFC_DLL_CTRL0); in rockchip_sfc_set_delay_lines()
256 writel(0, sfc->regbase + SFC_CTRL); in rockchip_sfc_init()
258 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); in rockchip_sfc_init()
267 sfc->regbase = dev_read_addr_ptr(bus); in rockchip_sfc_ofdata_to_platdata()
331 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, in rockchip_sfc_wait_txfifo_ready()
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H A Dcadence_qspi.c28 cadence_qspi_apb_config_baudrate_div(priv->regbase, in cadence_spi_write_speed()
32 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, in cadence_spi_write_speed()
43 void *base = priv->regbase; in spi_calibration()
129 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_speed()
147 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_speed()
159 priv->regbase = plat->regbase; in cadence_spi_probe()
175 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_mode()
178 cadence_qspi_apb_set_clk_mode(priv->regbase, mode); in cadence_spi_set_mode()
181 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_mode()
193 void *base = priv->regbase; in cadence_spi_xfer()
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/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-rockchip-sfc.c183 void __iomem *regbase; member
202 writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); in rockchip_sfc_reset()
204 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, in rockchip_sfc_reset()
211 writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR); in rockchip_sfc_reset()
220 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); in rockchip_sfc_get_version()
253 writel(val, sfc->regbase + SFC_DLL_CTRL0); in rockchip_sfc_set_delay_lines()
261 reg = readl(sfc->regbase + SFC_IMR); in rockchip_sfc_irq_unmask()
263 writel(reg, sfc->regbase + SFC_IMR); in rockchip_sfc_irq_unmask()
271 reg = readl(sfc->regbase + SFC_IMR); in rockchip_sfc_irq_mask()
273 writel(reg, sfc->regbase + SFC_IMR); in rockchip_sfc_irq_mask()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-pxa.c66 void __iomem *regbase; member
165 return bank->regbase; in gpio_bank_base()
347 struct device_node *np, void __iomem *regbase) in pxa_init_gpio_chip() argument
375 bank->regbase = regbase + BANK_OFF(i); in pxa_init_gpio_chip()
388 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; in update_edge_detect()
389 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; in update_edge_detect()
392 writel_relaxed(grer, c->regbase + GRER_OFFSET); in update_edge_detect()
393 writel_relaxed(gfer, c->regbase + GFER_OFFSET); in update_edge_detect()
416 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
419 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Dd11regs.h111 #define D11_REG32_ADDR(regbase, regname) \ argument
114 (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname)); \
116 #define D11_REG16_ADDR(regbase, regname) \ argument
119 (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname)); \
122 #define D11_REG32_ADDR(regbase, regname) \ argument
123 (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname))
124 #define D11_REG16_ADDR(regbase, regname) \ argument
125 (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname))
129 #define D11_REG32_ADDR_ENTRY(regbase, regname) \ argument
130 (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname))
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/OK3568_Linux_fs/kernel/drivers/mtd/spi-nor/controllers/
H A Dhisi-sfc.c93 void __iomem *regbase; member
107 return readl_poll_timeout(host->regbase + FMC_INT, reg, in hisi_spi_nor_wait_op_finish()
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG); in hisi_spi_nor_init()
187 writel(reg, host->regbase + FMC_CMD); in hisi_spi_nor_op_reg()
190 writel(reg, host->regbase + FMC_DATA_NUM); in hisi_spi_nor_op_reg()
193 writel(reg, host->regbase + FMC_OP_CFG); in hisi_spi_nor_op_reg()
195 writel(0xff, host->regbase + FMC_INT_CLR); in hisi_spi_nor_op_reg()
197 writel(reg, host->regbase + FMC_OP); in hisi_spi_nor_op_reg()
237 reg = readl(host->regbase + FMC_CFG); in hisi_spi_nor_dma_transfer()
242 writel(reg, host->regbase + FMC_CFG); in hisi_spi_nor_dma_transfer()
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