1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Serial Flash Controller Driver
4 *
5 * Copyright (c) 2017-2021, Rockchip Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Chris Morgan <macroalpha82@gmail.com>
8 * Jon Lin <Jon.lin@rock-chips.com>
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/iopoll.h>
17 #include <linux/interrupt.h>
18 #include <linux/mm.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/slab.h>
25 #include <linux/spi/spi-mem.h>
26
27 /* System control */
28 #define SFC_CTRL 0x0
29 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
30 #define SFC_CTRL_CMD_BITS_SHIFT 8
31 #define SFC_CTRL_ADDR_BITS_SHIFT 10
32 #define SFC_CTRL_DATA_BITS_SHIFT 12
33
34 /* Interrupt mask */
35 #define SFC_IMR 0x4
36 #define SFC_IMR_RX_FULL BIT(0)
37 #define SFC_IMR_RX_UFLOW BIT(1)
38 #define SFC_IMR_TX_OFLOW BIT(2)
39 #define SFC_IMR_TX_EMPTY BIT(3)
40 #define SFC_IMR_TRAN_FINISH BIT(4)
41 #define SFC_IMR_BUS_ERR BIT(5)
42 #define SFC_IMR_NSPI_ERR BIT(6)
43 #define SFC_IMR_DMA BIT(7)
44
45 /* Interrupt clear */
46 #define SFC_ICLR 0x8
47 #define SFC_ICLR_RX_FULL BIT(0)
48 #define SFC_ICLR_RX_UFLOW BIT(1)
49 #define SFC_ICLR_TX_OFLOW BIT(2)
50 #define SFC_ICLR_TX_EMPTY BIT(3)
51 #define SFC_ICLR_TRAN_FINISH BIT(4)
52 #define SFC_ICLR_BUS_ERR BIT(5)
53 #define SFC_ICLR_NSPI_ERR BIT(6)
54 #define SFC_ICLR_DMA BIT(7)
55
56 /* FIFO threshold level */
57 #define SFC_FTLR 0xc
58 #define SFC_FTLR_TX_SHIFT 0
59 #define SFC_FTLR_TX_MASK 0x1f
60 #define SFC_FTLR_RX_SHIFT 8
61 #define SFC_FTLR_RX_MASK 0x1f
62
63 /* Reset FSM and FIFO */
64 #define SFC_RCVR 0x10
65 #define SFC_RCVR_RESET BIT(0)
66
67 /* Enhanced mode */
68 #define SFC_AX 0x14
69
70 /* Address Bit number */
71 #define SFC_ABIT 0x18
72
73 /* Interrupt status */
74 #define SFC_ISR 0x1c
75 #define SFC_ISR_RX_FULL_SHIFT BIT(0)
76 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
77 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
78 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
79 #define SFC_ISR_TX_FINISH_SHIFT BIT(4)
80 #define SFC_ISR_BUS_ERR_SHIFT BIT(5)
81 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
82 #define SFC_ISR_DMA_SHIFT BIT(7)
83
84 /* FIFO status */
85 #define SFC_FSR 0x20
86 #define SFC_FSR_TX_IS_FULL BIT(0)
87 #define SFC_FSR_TX_IS_EMPTY BIT(1)
88 #define SFC_FSR_RX_IS_EMPTY BIT(2)
89 #define SFC_FSR_RX_IS_FULL BIT(3)
90 #define SFC_FSR_TXLV_MASK GENMASK(12, 8)
91 #define SFC_FSR_TXLV_SHIFT 8
92 #define SFC_FSR_RXLV_MASK GENMASK(20, 16)
93 #define SFC_FSR_RXLV_SHIFT 16
94
95 /* FSM status */
96 #define SFC_SR 0x24
97 #define SFC_SR_IS_IDLE 0x0
98 #define SFC_SR_IS_BUSY 0x1
99
100 /* Raw interrupt status */
101 #define SFC_RISR 0x28
102 #define SFC_RISR_RX_FULL BIT(0)
103 #define SFC_RISR_RX_UNDERFLOW BIT(1)
104 #define SFC_RISR_TX_OVERFLOW BIT(2)
105 #define SFC_RISR_TX_EMPTY BIT(3)
106 #define SFC_RISR_TRAN_FINISH BIT(4)
107 #define SFC_RISR_BUS_ERR BIT(5)
108 #define SFC_RISR_NSPI_ERR BIT(6)
109 #define SFC_RISR_DMA BIT(7)
110
111 /* Version */
112 #define SFC_VER 0x2C
113 #define SFC_VER_3 0x3
114 #define SFC_VER_4 0x4
115 #define SFC_VER_5 0x5
116 #define SFC_VER_6 0x6
117 #define SFC_VER_8 0x8
118
119 /* Delay line controller resiter */
120 #define SFC_DLL_CTRL0 0x3C
121 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
122 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
123 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
124
125 /* Master trigger */
126 #define SFC_DMA_TRIGGER 0x80
127 #define SFC_DMA_TRIGGER_START 1
128
129 /* Src or Dst addr for master */
130 #define SFC_DMA_ADDR 0x84
131
132 /* Length control register extension 32GB */
133 #define SFC_LEN_CTRL 0x88
134 #define SFC_LEN_CTRL_TRB_SEL 1
135 #define SFC_LEN_EXT 0x8C
136
137 /* Command */
138 #define SFC_CMD 0x100
139 #define SFC_CMD_IDX_SHIFT 0
140 #define SFC_CMD_DUMMY_SHIFT 8
141 #define SFC_CMD_DIR_SHIFT 12
142 #define SFC_CMD_DIR_RD 0
143 #define SFC_CMD_DIR_WR 1
144 #define SFC_CMD_ADDR_SHIFT 14
145 #define SFC_CMD_ADDR_0BITS 0
146 #define SFC_CMD_ADDR_24BITS 1
147 #define SFC_CMD_ADDR_32BITS 2
148 #define SFC_CMD_ADDR_XBITS 3
149 #define SFC_CMD_TRAN_BYTES_SHIFT 16
150 #define SFC_CMD_CS_SHIFT 30
151
152 /* Address */
153 #define SFC_ADDR 0x104
154
155 /* Data */
156 #define SFC_DATA 0x108
157
158 /* The controller and documentation reports that it supports up to 4 CS
159 * devices (0-3), however I have only been able to test a single CS (CS 0)
160 * due to the configuration of my device.
161 */
162 #define SFC_MAX_CHIPSELECT_NUM 4
163
164 #define SFC_MAX_IOSIZE_VER3 (512 * 31)
165 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
166
167 /* DMA is only enabled for large data transmission */
168 #define SFC_DMA_TRANS_THRETHOLD (0x40)
169
170 /* Maximum clock values from datasheet suggest keeping clock value under
171 * 150MHz. No minimum or average value is suggested.
172 */
173 #define SFC_MAX_SPEED (150 * 1000 * 1000)
174 #define SFC_DLL_THRESHOLD_RATE (50 * 1000 * 1000)
175
176 #define SFC_DLL_TRANING_STEP 10 /* Training step */
177 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Valid DLL winbow */
178
179 #define ROCKCHIP_AUTOSUSPEND_DELAY 2000
180
181 struct rockchip_sfc {
182 struct device *dev;
183 void __iomem *regbase;
184 struct clk *hclk;
185 struct clk *clk;
186 u32 frequency;
187 /* virtual mapped addr for dma_buffer */
188 void *buffer;
189 dma_addr_t dma_buffer;
190 struct completion cp;
191 bool use_dma;
192 u32 max_iosize;
193 u32 dll_cells;
194 u16 version;
195 };
196
rockchip_sfc_reset(struct rockchip_sfc * sfc)197 static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
198 {
199 int err;
200 u32 status;
201
202 writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
203
204 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
205 !(status & SFC_RCVR_RESET), 20,
206 jiffies_to_usecs(HZ));
207 if (err)
208 dev_err(sfc->dev, "SFC reset never finished\n");
209
210 /* Still need to clear the masked interrupt from RISR */
211 writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
212
213 dev_dbg(sfc->dev, "reset\n");
214
215 return err;
216 }
217
rockchip_sfc_get_version(struct rockchip_sfc * sfc)218 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
219 {
220 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
221 }
222
rockchip_sfc_get_max_iosize(struct rockchip_sfc * sfc)223 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
224 {
225 return SFC_MAX_IOSIZE_VER3;
226 }
227
rockchip_sfc_get_max_dll_cells(struct rockchip_sfc * sfc)228 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc)
229 {
230 switch (rockchip_sfc_get_version(sfc)) {
231 case SFC_VER_8:
232 case SFC_VER_6:
233 case SFC_VER_5:
234 return SFC_DLL_CTRL0_DLL_MAX_VER5;
235 case SFC_VER_4:
236 return SFC_DLL_CTRL0_DLL_MAX_VER4;
237 default:
238 return 0;
239 }
240 }
241
rockchip_sfc_set_delay_lines(struct rockchip_sfc * sfc,u16 cells)242 static void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells)
243 {
244 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc);
245 u32 val = 0;
246
247 if (cells > cell_max)
248 cells = cell_max;
249
250 if (cells)
251 val = SFC_DLL_CTRL0_SCLK_SMP_DLL | cells;
252
253 writel(val, sfc->regbase + SFC_DLL_CTRL0);
254 }
255
rockchip_sfc_irq_unmask(struct rockchip_sfc * sfc,u32 mask)256 static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask)
257 {
258 u32 reg;
259
260 /* Enable transfer complete interrupt */
261 reg = readl(sfc->regbase + SFC_IMR);
262 reg &= ~mask;
263 writel(reg, sfc->regbase + SFC_IMR);
264 }
265
rockchip_sfc_irq_mask(struct rockchip_sfc * sfc,u32 mask)266 static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask)
267 {
268 u32 reg;
269
270 /* Disable transfer finish interrupt */
271 reg = readl(sfc->regbase + SFC_IMR);
272 reg |= mask;
273 writel(reg, sfc->regbase + SFC_IMR);
274 }
275
rockchip_sfc_init(struct rockchip_sfc * sfc)276 static int rockchip_sfc_init(struct rockchip_sfc *sfc)
277 {
278 writel(0, sfc->regbase + SFC_CTRL);
279 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
280 rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF);
281 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
282 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
283
284 return 0;
285 }
286
rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc * sfc,u32 timeout_us)287 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
288 {
289 int ret = 0;
290 u32 status;
291
292 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
293 status & SFC_FSR_TXLV_MASK, 0,
294 timeout_us);
295 if (ret) {
296 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");
297
298 return -ETIMEDOUT;
299 }
300
301 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
302 }
303
rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc * sfc,u32 timeout_us)304 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
305 {
306 int ret = 0;
307 u32 status;
308
309 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
310 status & SFC_FSR_RXLV_MASK, 0,
311 timeout_us);
312 if (ret) {
313 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");
314
315 return -ETIMEDOUT;
316 }
317
318 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
319 }
320
rockchip_sfc_adjust_op_work(struct spi_mem_op * op)321 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
322 {
323 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
324 /*
325 * SFC not support output DUMMY cycles right after CMD cycles, so
326 * treat it as ADDR cycles.
327 */
328 op->addr.nbytes = op->dummy.nbytes;
329 op->addr.buswidth = op->dummy.buswidth;
330 op->addr.val = 0xFFFFFFFFF;
331
332 op->dummy.nbytes = 0;
333 }
334 }
335
rockchip_sfc_xfer_setup(struct rockchip_sfc * sfc,struct spi_mem * mem,const struct spi_mem_op * op,u32 len)336 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
337 struct spi_mem *mem,
338 const struct spi_mem_op *op,
339 u32 len)
340 {
341 u32 ctrl = 0, cmd = 0;
342
343 /* set CMD */
344 cmd = op->cmd.opcode;
345 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
346
347 /* set ADDR */
348 if (op->addr.nbytes) {
349 if (op->addr.nbytes == 4) {
350 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
351 } else if (op->addr.nbytes == 3) {
352 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
353 } else {
354 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
355 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
356 }
357
358 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
359 }
360
361 /* set DUMMY */
362 if (op->dummy.nbytes) {
363 if (op->dummy.buswidth == 4)
364 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
365 else if (op->dummy.buswidth == 2)
366 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
367 else
368 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
369 }
370
371 /* set DATA */
372 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
373 writel(len, sfc->regbase + SFC_LEN_EXT);
374 else
375 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
376 if (len) {
377 if (op->data.dir == SPI_MEM_DATA_OUT)
378 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
379
380 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
381 }
382 if (!len && op->addr.nbytes)
383 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
384
385 /* set the Controller */
386 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
387 cmd |= mem->spi->chip_select << SFC_CMD_CS_SHIFT;
388
389 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
390 op->addr.nbytes, op->addr.buswidth,
391 op->dummy.nbytes, op->dummy.buswidth);
392 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
393 ctrl, cmd, op->addr.val, len);
394
395 writel(ctrl, sfc->regbase + SFC_CTRL);
396 writel(cmd, sfc->regbase + SFC_CMD);
397 if (op->addr.nbytes)
398 writel(op->addr.val, sfc->regbase + SFC_ADDR);
399
400 return 0;
401 }
402
rockchip_sfc_write_fifo(struct rockchip_sfc * sfc,const u8 * buf,int len)403 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
404 {
405 u8 bytes = len & 0x3;
406 u32 dwords;
407 int tx_level;
408 u32 write_words;
409 u32 tmp = 0;
410
411 dwords = len >> 2;
412 while (dwords) {
413 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
414 if (tx_level < 0)
415 return tx_level;
416 write_words = min_t(u32, tx_level, dwords);
417 iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words);
418 buf += write_words << 2;
419 dwords -= write_words;
420 }
421
422 /* write the rest non word aligned bytes */
423 if (bytes) {
424 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
425 if (tx_level < 0)
426 return tx_level;
427 memcpy(&tmp, buf, bytes);
428 writel(tmp, sfc->regbase + SFC_DATA);
429 }
430
431 return len;
432 }
433
rockchip_sfc_read_fifo(struct rockchip_sfc * sfc,u8 * buf,int len)434 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
435 {
436 u8 bytes = len & 0x3;
437 u32 dwords;
438 u8 read_words;
439 int rx_level;
440 int tmp;
441
442 /* word aligned access only */
443 dwords = len >> 2;
444 while (dwords) {
445 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
446 if (rx_level < 0)
447 return rx_level;
448 read_words = min_t(u32, rx_level, dwords);
449 ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words);
450 buf += read_words << 2;
451 dwords -= read_words;
452 }
453
454 /* read the rest non word aligned bytes */
455 if (bytes) {
456 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
457 if (rx_level < 0)
458 return rx_level;
459 tmp = readl(sfc->regbase + SFC_DATA);
460 memcpy(buf, &tmp, bytes);
461 }
462
463 return len;
464 }
465
rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc * sfc,dma_addr_t dma_buf,size_t len)466 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
467 {
468 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
469 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
470 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
471
472 return len;
473 }
474
rockchip_sfc_xfer_data_poll(struct rockchip_sfc * sfc,const struct spi_mem_op * op,u32 len)475 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
476 const struct spi_mem_op *op, u32 len)
477 {
478 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
479
480 if (op->data.dir == SPI_MEM_DATA_OUT)
481 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
482 else
483 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
484 }
485
rockchip_sfc_xfer_data_dma(struct rockchip_sfc * sfc,const struct spi_mem_op * op,u32 len)486 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
487 const struct spi_mem_op *op, u32 len)
488 {
489 int ret;
490
491 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
492
493 if (op->data.dir == SPI_MEM_DATA_OUT)
494 memcpy(sfc->buffer, op->data.buf.out, len);
495
496 ret = rockchip_sfc_fifo_transfer_dma(sfc, sfc->dma_buffer, len);
497 if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) {
498 dev_err(sfc->dev, "DMA wait for transfer finish timeout\n");
499 ret = -ETIMEDOUT;
500 }
501 rockchip_sfc_irq_mask(sfc, SFC_IMR_DMA);
502 if (op->data.dir == SPI_MEM_DATA_IN)
503 memcpy(op->data.buf.in, sfc->buffer, len);
504
505 return ret;
506 }
507
rockchip_sfc_xfer_done(struct rockchip_sfc * sfc,u32 timeout_us)508 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
509 {
510 int ret = 0;
511 u32 status;
512
513 /*
514 * There is very little data left in fifo, and the controller will
515 * complete the transmission in a short period of time.
516 */
517 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
518 !(status & SFC_SR_IS_BUSY),
519 0, 10);
520 if (!ret)
521 return 0;
522
523 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
524 !(status & SFC_SR_IS_BUSY),
525 20, timeout_us);
526 if (ret) {
527 dev_err(sfc->dev, "wait sfc idle timeout\n");
528 rockchip_sfc_reset(sfc);
529
530 ret = -EIO;
531 }
532
533 return ret;
534 }
535
rockchip_sfc_exec_op_bypass(struct rockchip_sfc * sfc,struct spi_mem * mem,const struct spi_mem_op * op)536 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc,
537 struct spi_mem *mem,
538 const struct spi_mem_op *op)
539 {
540 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
541 u32 ret;
542
543 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
544 rockchip_sfc_xfer_setup(sfc, mem, op, len);
545 ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
546 if (ret != len) {
547 dev_err(sfc->dev, "xfer data failed ret %d\n", ret);
548
549 return -EIO;
550 }
551
552 return rockchip_sfc_xfer_done(sfc, 100000);
553 }
554
rockchip_sfc_delay_lines_tuning(struct rockchip_sfc * sfc,struct spi_mem * mem)555 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_mem *mem)
556 {
557 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
558 SPI_MEM_OP_NO_ADDR,
559 SPI_MEM_OP_NO_DUMMY,
560 SPI_MEM_OP_DATA_IN(3, NULL, 1));
561 u8 id[3], id_temp[3];
562 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc);
563 u16 right, left = 0;
564 u16 step = SFC_DLL_TRANING_STEP;
565 bool dll_valid = false;
566
567 clk_set_rate(sfc->clk, SFC_DLL_THRESHOLD_RATE);
568 op.data.buf.in = &id;
569 rockchip_sfc_exec_op_bypass(sfc, mem, &op);
570 if ((0xFF == id[0] && 0xFF == id[1]) ||
571 (0x00 == id[0] && 0x00 == id[1])) {
572 dev_dbg(sfc->dev, "no dev, dll by pass\n");
573 clk_set_rate(sfc->clk, mem->spi->max_speed_hz);
574
575 return;
576 }
577
578 clk_set_rate(sfc->clk, mem->spi->max_speed_hz);
579 op.data.buf.in = &id_temp;
580 for (right = 0; right <= cell_max; right += step) {
581 int ret;
582
583 rockchip_sfc_set_delay_lines(sfc, right);
584 rockchip_sfc_exec_op_bypass(sfc, mem, &op);
585 dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n",
586 id_temp[0], id_temp[1], id_temp[2]);
587
588 ret = memcmp(&id, &id_temp, 3);
589 if (dll_valid && ret) {
590 right -= step;
591
592 break;
593 }
594 if (!dll_valid && !ret)
595 left = right;
596
597 if (!ret)
598 dll_valid = true;
599
600 /* Add cell_max to loop */
601 if (right == cell_max)
602 break;
603 if (right + step > cell_max)
604 right = cell_max - step;
605 }
606
607 if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) {
608 if (left == 0 && right < cell_max)
609 sfc->dll_cells = left + (right - left) * 2 / 5;
610 else
611 sfc->dll_cells = left + (right - left) / 2;
612 } else {
613 sfc->dll_cells = 0;
614 }
615
616 if (sfc->dll_cells) {
617 dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n",
618 left, right, sfc->dll_cells, mem->spi->max_speed_hz,
619 rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc));
620 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells);
621 } else {
622 dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the frequency\n",
623 left, right, mem->spi->max_speed_hz);
624 rockchip_sfc_set_delay_lines(sfc, 0);
625 clk_set_rate(sfc->clk, SFC_DLL_THRESHOLD_RATE);
626 mem->spi->max_speed_hz = clk_get_rate(sfc->clk);
627 }
628 }
629
rockchip_sfc_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)630 static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
631 {
632 struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master);
633 u32 len = op->data.nbytes;
634 int ret;
635
636 ret = pm_runtime_get_sync(sfc->dev);
637 if (ret < 0) {
638 pm_runtime_put_noidle(sfc->dev);
639 return ret;
640 }
641
642 if (unlikely(mem->spi->max_speed_hz != sfc->frequency) && !has_acpi_companion(sfc->dev)) {
643 ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz);
644 if (ret)
645 goto out;
646 sfc->frequency = mem->spi->max_speed_hz;
647 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) {
648 if (clk_get_rate(sfc->clk) > SFC_DLL_THRESHOLD_RATE)
649 rockchip_sfc_delay_lines_tuning(sfc, mem);
650 else
651 rockchip_sfc_set_delay_lines(sfc, 0);
652 }
653
654 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n",
655 sfc->frequency, clk_get_rate(sfc->clk));
656 }
657
658 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
659 rockchip_sfc_xfer_setup(sfc, mem, op, len);
660 if (len) {
661 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD && !(len & 0x3)) {
662 init_completion(&sfc->cp);
663 rockchip_sfc_irq_unmask(sfc, SFC_IMR_DMA);
664 ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
665 } else {
666 ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
667 }
668
669 if (ret != len) {
670 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
671
672 ret = -EIO;
673 goto out;
674 }
675 }
676
677 ret = rockchip_sfc_xfer_done(sfc, 100000);
678 out:
679 pm_runtime_mark_last_busy(sfc->dev);
680 pm_runtime_put_autosuspend(sfc->dev);
681
682 return ret;
683 }
684
rockchip_sfc_adjust_op_size(struct spi_mem * mem,struct spi_mem_op * op)685 static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
686 {
687 struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master);
688
689 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
690
691 return 0;
692 }
693
694 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
695 .exec_op = rockchip_sfc_exec_mem_op,
696 .adjust_op_size = rockchip_sfc_adjust_op_size,
697 };
698
rockchip_sfc_irq_handler(int irq,void * dev_id)699 static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id)
700 {
701 struct rockchip_sfc *sfc = dev_id;
702 u32 reg;
703
704 reg = readl(sfc->regbase + SFC_RISR);
705
706 /* Clear interrupt */
707 writel_relaxed(reg, sfc->regbase + SFC_ICLR);
708
709 if (reg & SFC_RISR_DMA) {
710 complete(&sfc->cp);
711
712 return IRQ_HANDLED;
713 }
714
715 return IRQ_NONE;
716 }
717
rockchip_sfc_probe(struct platform_device * pdev)718 static int rockchip_sfc_probe(struct platform_device *pdev)
719 {
720 struct device *dev = &pdev->dev;
721 struct spi_master *master;
722 struct resource *res;
723 struct rockchip_sfc *sfc;
724 int ret;
725
726 master = devm_spi_alloc_master(&pdev->dev, sizeof(*sfc));
727 if (!master)
728 return -ENOMEM;
729
730 master->flags = SPI_MASTER_HALF_DUPLEX;
731 master->mem_ops = &rockchip_sfc_mem_ops;
732 master->dev.of_node = pdev->dev.of_node;
733 master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL;
734 master->max_speed_hz = SFC_MAX_SPEED;
735 master->num_chipselect = SFC_MAX_CHIPSELECT_NUM;
736
737 sfc = spi_master_get_devdata(master);
738 sfc->dev = dev;
739
740 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
741 sfc->regbase = devm_ioremap_resource(dev, res);
742 if (IS_ERR(sfc->regbase))
743 return PTR_ERR(sfc->regbase);
744
745 if (!has_acpi_companion(&pdev->dev))
746 sfc->clk = devm_clk_get(&pdev->dev, "clk_sfc");
747 if (IS_ERR(sfc->clk)) {
748 dev_err(&pdev->dev, "Failed to get sfc interface clk\n");
749 return PTR_ERR(sfc->clk);
750 }
751
752 if (!has_acpi_companion(&pdev->dev))
753 sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc");
754 if (IS_ERR(sfc->hclk)) {
755 dev_err(&pdev->dev, "Failed to get sfc ahb clk\n");
756 return PTR_ERR(sfc->hclk);
757 }
758
759 if (has_acpi_companion(&pdev->dev)) {
760 ret = device_property_read_u32(&pdev->dev, "clock-frequency", &sfc->frequency);
761 if (ret) {
762 dev_err(&pdev->dev, "Failed to find clock-frequency in ACPI\n");
763 return ret;
764 }
765 }
766
767 sfc->use_dma = !of_property_read_bool(sfc->dev->of_node,
768 "rockchip,sfc-no-dma");
769
770 if (sfc->use_dma) {
771 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
772 if (ret) {
773 dev_warn(dev, "Unable to set dma mask\n");
774 return ret;
775 }
776
777 sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_IOSIZE_VER3,
778 &sfc->dma_buffer,
779 GFP_KERNEL);
780 if (!sfc->buffer)
781 return -ENOMEM;
782 }
783
784 ret = clk_prepare_enable(sfc->hclk);
785 if (ret) {
786 dev_err(&pdev->dev, "Failed to enable ahb clk\n");
787 goto err_hclk;
788 }
789
790 ret = clk_prepare_enable(sfc->clk);
791 if (ret) {
792 dev_err(&pdev->dev, "Failed to enable interface clk\n");
793 goto err_clk;
794 }
795
796 /* Find the irq */
797 ret = platform_get_irq(pdev, 0);
798 if (ret < 0) {
799 dev_err(dev, "Failed to get the irq\n");
800 goto err_irq;
801 }
802
803 ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler,
804 0, pdev->name, sfc);
805 if (ret) {
806 dev_err(dev, "Failed to request irq\n");
807
808 return ret;
809 }
810
811 platform_set_drvdata(pdev, sfc);
812
813 if (IS_ENABLED(CONFIG_ROCKCHIP_THUNDER_BOOT)) {
814 u32 status;
815
816 if (readl_poll_timeout(sfc->regbase + SFC_SR, status,
817 !(status & SFC_SR_IS_BUSY), 10,
818 500 * USEC_PER_MSEC))
819 dev_err(dev, "Wait for SFC idle timeout!\n");
820 }
821
822 ret = rockchip_sfc_init(sfc);
823 if (ret)
824 goto err_irq;
825
826 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
827 sfc->version = rockchip_sfc_get_version(sfc);
828
829 pm_runtime_set_autosuspend_delay(dev, ROCKCHIP_AUTOSUSPEND_DELAY);
830 pm_runtime_use_autosuspend(dev);
831 pm_runtime_set_active(dev);
832 pm_runtime_enable(dev);
833 pm_runtime_get_noresume(dev);
834
835 ret = spi_register_master(master);
836 if (ret)
837 goto err_register;
838
839 pm_runtime_mark_last_busy(dev);
840 pm_runtime_put_autosuspend(dev);
841
842 return 0;
843
844 err_register:
845 pm_runtime_disable(sfc->dev);
846 pm_runtime_set_suspended(sfc->dev);
847 pm_runtime_dont_use_autosuspend(sfc->dev);
848 err_irq:
849 clk_disable_unprepare(sfc->clk);
850 err_clk:
851 clk_disable_unprepare(sfc->hclk);
852 err_hclk:
853 return ret;
854 }
855
rockchip_sfc_remove(struct platform_device * pdev)856 static int rockchip_sfc_remove(struct platform_device *pdev)
857 {
858 struct spi_master *master = platform_get_drvdata(pdev);
859 struct rockchip_sfc *sfc = platform_get_drvdata(pdev);
860
861 spi_unregister_master(master);
862
863 clk_disable_unprepare(sfc->clk);
864 clk_disable_unprepare(sfc->hclk);
865
866 return 0;
867 }
868
rockchip_sfc_runtime_suspend(struct device * dev)869 static int __maybe_unused rockchip_sfc_runtime_suspend(struct device *dev)
870 {
871 struct rockchip_sfc *sfc = dev_get_drvdata(dev);
872
873 clk_disable_unprepare(sfc->clk);
874 clk_disable_unprepare(sfc->hclk);
875
876 return 0;
877 }
878
rockchip_sfc_runtime_resume(struct device * dev)879 static int __maybe_unused rockchip_sfc_runtime_resume(struct device *dev)
880 {
881 struct rockchip_sfc *sfc = dev_get_drvdata(dev);
882 int ret;
883
884 ret = clk_prepare_enable(sfc->hclk);
885 if (ret < 0)
886 return ret;
887
888 ret = clk_prepare_enable(sfc->clk);
889 if (ret < 0)
890 clk_disable_unprepare(sfc->hclk);
891
892 return ret;
893 }
894
rockchip_sfc_suspend(struct device * dev)895 static int __maybe_unused rockchip_sfc_suspend(struct device *dev)
896 {
897 pinctrl_pm_select_sleep_state(dev);
898
899 return pm_runtime_force_suspend(dev);
900 }
901
rockchip_sfc_resume(struct device * dev)902 static int __maybe_unused rockchip_sfc_resume(struct device *dev)
903 {
904 struct rockchip_sfc *sfc = dev_get_drvdata(dev);
905 int ret;
906
907 ret = pm_runtime_force_resume(dev);
908 if (ret < 0)
909 return ret;
910
911 pinctrl_pm_select_default_state(dev);
912
913 ret = pm_runtime_get_sync(dev);
914 if (ret < 0) {
915 pm_runtime_put_noidle(dev);
916 return ret;
917 }
918
919 rockchip_sfc_init(sfc);
920 if (sfc->dll_cells)
921 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells);
922
923 pm_runtime_mark_last_busy(dev);
924 pm_runtime_put_autosuspend(dev);
925
926 return 0;
927 }
928
929 static const struct dev_pm_ops rockchip_sfc_pm_ops = {
930 SET_RUNTIME_PM_OPS(rockchip_sfc_runtime_suspend,
931 rockchip_sfc_runtime_resume, NULL)
932 SET_SYSTEM_SLEEP_PM_OPS(rockchip_sfc_suspend, rockchip_sfc_resume)
933 };
934
935 static const struct of_device_id rockchip_sfc_dt_ids[] = {
936 { .compatible = "rockchip,sfc"},
937 { /* sentinel */ }
938 };
939 MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids);
940
941 static struct platform_driver rockchip_sfc_driver = {
942 .driver = {
943 .name = "rockchip-sfc",
944 .of_match_table = rockchip_sfc_dt_ids,
945 .pm = &rockchip_sfc_pm_ops,
946 },
947 .probe = rockchip_sfc_probe,
948 .remove = rockchip_sfc_remove,
949 };
950 module_platform_driver(rockchip_sfc_driver);
951
952 MODULE_LICENSE("GPL v2");
953 MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver");
954 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
955 MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>");
956 MODULE_AUTHOR("Jon Lin <Jon.lin@rock-chips.com>");
957