54 static void gpio_bit_op(void __iomem *regbase, unsigned int offset,  in gpio_bit_op()  argument
63 	writel(val, regbase + offset);  in gpio_bit_op()
66 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit)  in gpio_bit_rd()  argument
71 	return readl(regbase + offset) & bit ? 1 : 0;  in gpio_bit_rd()
74 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit)  in gpio_irq_unmask()  argument
76 	gpio_bit_op(regbase, GPIO_INTEN, bit, 1);  in gpio_irq_unmask()
79 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit)  in gpio_irq_mask()  argument
81 	gpio_bit_op(regbase, GPIO_INTEN, bit, 0);  in gpio_irq_mask()
84 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit)  in gpio_irq_ack()  argument
86 	gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);  in gpio_irq_ack()
95 	isr = readl(bank->regbase + GPIO_INT_STATUS);  in generic_gpio_handle_irq()
96 	ilr_l = readl(bank->regbase + GPIO_INTTYPE_LEVEL_L);  in generic_gpio_handle_irq()
97 	ilr_h = readl(bank->regbase + GPIO_INTTYPE_LEVEL_H);  in generic_gpio_handle_irq()
104 		gpio_irq_mask(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
105 		gpio_irq_ack(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
114 				gpio_irq_unmask(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
120 				gpio_irq_unmask(bank->regbase, offset_to_bit(h_pin));  in generic_gpio_handle_irq()
128 			gpio_irq_unmask(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
132 static void gpio_set_intr_type(void __iomem *regbase,  in gpio_set_intr_type()  argument
138 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);  in gpio_set_intr_type()
139 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);  in gpio_set_intr_type()
142 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);  in gpio_set_intr_type()
143 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);  in gpio_set_intr_type()
146 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);  in gpio_set_intr_type()
147 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);  in gpio_set_intr_type()
150 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);  in gpio_set_intr_type()
151 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);  in gpio_set_intr_type()
156 static int gpio_get_intr_type(void __iomem *regbase,  in gpio_get_intr_type()  argument
162 	polarity = gpio_bit_rd(regbase, GPIO_INT_POLARITY, bit);  in gpio_get_intr_type()
163 	level = gpio_bit_rd(regbase, GPIO_INTTYPE_LEVEL, bit);  in gpio_get_intr_type()
217 	gpio_bit_op(bank->regbase, GPIO_SWPORT_DDR,  in gpio_irq_set_type()
219 	gpio_set_intr_type(bank->regbase, offset_to_bit(gpio), int_type);  in gpio_irq_set_type()
238 	type = gpio_get_intr_type(bank->regbase, offset_to_bit(gpio));  in gpio_irq_revert_type()
256 	gpio_set_intr_type(bank->regbase, offset_to_bit(gpio), int_type);  in gpio_irq_revert_type()
274 	return readl(bank->regbase + GPIO_EXT_PORT) & offset_to_bit(gpio) ? 1 : 0;  in gpio_irq_get_gpio_level()
289 	gpio_irq_unmask(bank->regbase, offset_to_bit(gpio));  in gpio_irq_enable()
313 	gpio_irq_mask(bank->regbase, offset_to_bit(gpio));  in gpio_irq_disable()
339 			writel(0xffff0000, bank->regbase + GPIO_INTEN_L);  in gpio_irq_init()
340 			writel(0xffff0000, bank->regbase + GPIO_INTEN_H);  in gpio_irq_init()