51 static void gpio_bit_op(void __iomem *regbase, unsigned int offset,  in gpio_bit_op()  argument
54 	u32 val = readl(regbase + offset);  in gpio_bit_op()
61 	writel(val, regbase + offset);  in gpio_bit_op()
64 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit)  in gpio_bit_rd()  argument
66 	return readl(regbase + offset) & bit ? 1 : 0;  in gpio_bit_rd()
69 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit)  in gpio_irq_unmask()  argument
71 	gpio_bit_op(regbase, GPIO_INTEN, bit, 1);  in gpio_irq_unmask()
74 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit)  in gpio_irq_mask()  argument
76 	gpio_bit_op(regbase, GPIO_INTEN, bit, 0);  in gpio_irq_mask()
79 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit)  in gpio_irq_ack()  argument
81 	gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);  in gpio_irq_ack()
90 	isr = readl(bank->regbase + GPIO_INT_STATUS);  in generic_gpio_handle_irq()
91 	ilr = readl(bank->regbase + GPIO_INTTYPE_LEVEL);  in generic_gpio_handle_irq()
99 		gpio_irq_mask(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
100 		gpio_irq_ack(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
108 			gpio_irq_unmask(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
116 			gpio_irq_unmask(bank->regbase, offset_to_bit(pin));  in generic_gpio_handle_irq()
120 static void gpio_set_intr_type(void __iomem *regbase,  in gpio_set_intr_type()  argument
126 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);  in gpio_set_intr_type()
127 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);  in gpio_set_intr_type()
130 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);  in gpio_set_intr_type()
131 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);  in gpio_set_intr_type()
134 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);  in gpio_set_intr_type()
135 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);  in gpio_set_intr_type()
138 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);  in gpio_set_intr_type()
139 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);  in gpio_set_intr_type()
144 static int gpio_get_intr_type(void __iomem *regbase,  in gpio_get_intr_type()  argument
150 	polarity = gpio_bit_rd(regbase, GPIO_INT_POLARITY, bit);  in gpio_get_intr_type()
151 	level = gpio_bit_rd(regbase, GPIO_INTTYPE_LEVEL, bit);  in gpio_get_intr_type()
205 	gpio_bit_op(bank->regbase, GPIO_SWPORT_DDR,  in gpio_irq_set_type()
207 	gpio_set_intr_type(bank->regbase, offset_to_bit(gpio), int_type);  in gpio_irq_set_type()
226 	type = gpio_get_intr_type(bank->regbase, offset_to_bit(gpio));  in gpio_irq_revert_type()
244 	gpio_set_intr_type(bank->regbase, offset_to_bit(gpio), int_type);  in gpio_irq_revert_type()
261 	return gpio_bit_rd(bank->regbase, GPIO_EXT_PORT, offset_to_bit(gpio));  in gpio_irq_get_gpio_level()
276 	gpio_irq_unmask(bank->regbase, offset_to_bit(gpio));  in gpio_irq_enable()
300 	gpio_irq_mask(bank->regbase, offset_to_bit(gpio));  in gpio_irq_disable()
326 			writel(0, bank->regbase + GPIO_INTEN);  in gpio_irq_init()