380 	cadence_qspi_apb_controller_disable(plat->regbase);  in cadence_qspi_apb_controller_init()
383 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
389 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
392 	writel(0, plat->regbase + CQSPI_REG_REMAP);  in cadence_qspi_apb_controller_init()
395 	writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);  in cadence_qspi_apb_controller_init()
398 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);  in cadence_qspi_apb_controller_init()
400 	cadence_qspi_apb_controller_enable(plat->regbase);  in cadence_qspi_apb_controller_init()
556 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_read_setup()
567 	writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);  in cadence_qspi_apb_indirect_read_setup()
577 		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
579 		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
592 	writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_indirect_read_setup()
595 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
598 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
604 	u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);  in cadence_qspi_get_rd_sram_level()
631 	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);  in cadence_qspi_apb_indirect_read_execute()
635 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
666 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,  in cadence_qspi_apb_indirect_read_execute()
675 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
682 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
700 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_write_setup()
704 	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);  in cadence_qspi_apb_indirect_write_setup()
708 	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);  in cadence_qspi_apb_indirect_write_setup()
710 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
713 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
726 	writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);  in cadence_qspi_apb_indirect_write_execute()
730 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
740 		ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,  in cadence_qspi_apb_indirect_write_execute()
753 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,  in cadence_qspi_apb_indirect_write_execute()
762 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
768 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()