| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk.h | 667 int div_offset, u8 div_shift,
692 int div_shift, int div_width,
702 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
752 u8 div_shift; member
775 .div_shift = ds, \
797 .div_shift = ds, \
819 .div_shift = ds, \
837 .div_shift = ds, \
855 .div_shift = ds, \
895 .div_shift = ds, \
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| H A D | clk-ddr.c | 27 int div_shift; member
183 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
228 ddrclk->div_shift = div_shift; in rockchip_clk_register_ddrclk()
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| H A D | clk.c | 42 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
96 div->shift = div_shift; in rockchip_clk_register_branch()
522 list->div_shift, list->div_width, in rockchip_clk_register_branches()
529 list->div_shift, list->div_width, in rockchip_clk_register_branches()
547 list->div_shift, list->div_width, in rockchip_clk_register_branches()
575 list->div_shift, list->div_width, in rockchip_clk_register_branches()
585 list->div_shift in rockchip_clk_register_branches()
594 list->div_shift, list->div_flags, &ctx->lock); in rockchip_clk_register_branches()
601 list->div_shift, list->div_width, in rockchip_clk_register_branches()
610 list->mux_width, list->div_shift, in rockchip_clk_register_branches()
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| H A D | clk-pvtm.c | 33 u32 div_shift; member
148 wr_msk_bit(div, pvtm->info->div_shift, in rockchip_clock_pvtm_init_freq()
204 .div_shift = 2,
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| H A D | clk-dclk-divider.c | 97 int div_offset, u8 div_shift, in rockchip_clk_register_dclk_branch() argument
149 div->shift = div_shift; in rockchip_clk_register_dclk_branch()
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| H A D | clk-half-divider.c | 155 int div_offset, u8 div_shift, in rockchip_clk_register_halfdiv() argument
204 div->shift = div_shift; in rockchip_clk_register_halfdiv()
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| H A D | clk-cpu.c | 502 int div_offset, u8 div_shift, in rockchip_clk_register_cpuclk_v2() argument
541 div->shift = div_shift; in rockchip_clk_register_cpuclk_v2()
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3528.c | 1051 u32 div_mask, div_shift; in rk3528_dclk_vop_get_clk() local
1063 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; in rk3528_dclk_vop_get_clk()
1071 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; in rk3528_dclk_vop_get_clk()
1079 div = (con & div_mask) >> div_shift; in rk3528_dclk_vop_get_clk()
1093 u32 div_mask, div_shift; in rk3528_dclk_vop_set_clk() local
1105 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; in rk3528_dclk_vop_set_clk()
1113 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; in rk3528_dclk_vop_set_clk()
1128 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; in rk3528_dclk_vop_set_clk()
1137 u32 sel_shift, sel_mask, div_shift, div_mask; in rk3528_uart_get_rate() local
1146 div_shift = CLK_UART0_SRC_DIV_SHIFT; in rk3528_uart_get_rate()
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| H A D | clk_rk3399.c | 670 uint8_t div_shift; member
682 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
685 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
688 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
691 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
694 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
714 div = bitfield_extract(val, spiclk->div_shift, in rk3399_spi_get_clk()
739 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | in rk3399_spi_set_clk()
741 ((src_clk_div << spiclk->div_shift) | in rk3399_spi_set_clk()
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| H A D | clk_rk3368.c | 496 uint8_t div_shift; member
504 [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
505 [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
506 [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
530 div = extract_bits(val, 7, spiclk->div_shift); in rk3368_spi_get_clk()
555 ((0x7f << spiclk->div_shift) | in rk3368_spi_set_clk()
557 ((src_clk_div << spiclk->div_shift) | in rk3368_spi_set_clk()
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| H A D | clk_rk3588.c | 1114 u32 mask, div_shift, sel_shift; in rk3588_dclk_vop_set_clk() local
1123 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1132 div_shift = DCLK1_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1141 div_shift = DCLK2_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1149 div_shift = DCLK3_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1164 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1170 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1211 (best_div - 1) << div_shift); in rk3588_dclk_vop_set_clk()
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/ |
| H A D | clk-regmap.h | 128 u8 div_shift; member
149 .div_shift = _div_shift, \
166 .div_shift = _div_shift, \
303 u32 div_reg, u8 div_shift, u8 div_width,
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| H A D | clk-regmap-composite.c | 210 u32 div_reg, u8 div_shift, u8 div_width, in devm_clk_regmap_register_composite() argument
264 div->shift = div_shift; in devm_clk_regmap_register_composite()
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| /OK3568_Linux_fs/kernel/drivers/clk/x86/ |
| H A D | clk-cgu.h | 187 u8 div_shift; member
235 .div_shift = _shift, \
275 .div_shift = _shift, \
295 .div_shift = _shift, \
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| H A D | clk-cgu.c | 31 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
220 u8 shift = list->div_shift; in lgm_clk_register_divider()
278 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed_factor()
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 52 u32 div_shift; member
114 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
142 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
143 val |= (div << pll->div_shift); in clk_pllv3_set_rate()
438 pll->div_shift = 1; in imx_clk_hw_pllv3()
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| /OK3568_Linux_fs/kernel/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 184 unsigned char div_shift; member
195 .div_shift = _shift, \
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| H A D | clk-mt8167.c | 662 .div_shift = _shift, \
692 .div_shift = _shift, \
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | clk-bm1880.c | 120 s8 div_shift; member
152 .div_shift = _div_shift, \
168 .div_shift = -1, \
803 if (clks->div_shift >= 0) { in bm1880_clk_register_composite()
812 div_hws->div.shift = clks->div_shift; in bm1880_clk_register_composite()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 67 u8 div_shift; member
286 vop2_clk->div.shift = branch->div_shift; in vop2_clk_register()
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-s3c2410-dclk.c | 174 int div_shift, int cmp_shift) in s3c24xx_dclk_update_cmp() argument
183 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1; in s3c24xx_dclk_update_cmp()
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| /OK3568_Linux_fs/kernel/drivers/clk/at91/ |
| H A D | clk-sam9x60-pll.c | 253 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_prepare()
261 (div->div << core->layout->div_shift) | in sam9x60_div_pll_prepare()
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| H A D | pmc.h | 63 u8 div_shift; member
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| /OK3568_Linux_fs/kernel/drivers/mfd/ |
| H A D | db8500-prcmu.c | 524 u32 div_shift; member
531 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
536 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
541 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
1535 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
1900 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); in set_dsiescclk_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/tegra/ |
| H A D | clk-tegra-periph.c | 836 u8 div_shift; member
847 .div_shift = _div_shift,\
971 data->div_shift, 8, 1, data->lock); in init_pllp()
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