1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
8 *
9 * based on
10 *
11 * samsung/clk.c
12 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
13 * Copyright (c) 2013 Linaro Ltd.
14 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 */
16
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/io.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/regmap.h>
23 #include <linux/reboot.h>
24 #include <linux/rational.h>
25 #include "clk.h"
26
27 /**
28 * Register a clock branch.
29 * Most clock branches have a form like
30 *
31 * src1 --|--\
32 * |M |--[GATE]-[DIV]-
33 * src2 --|--/
34 *
35 * sometimes without one of those components.
36 */
rockchip_clk_register_branch(const char * name,const char * const * parent_names,u8 num_parents,void __iomem * base,int muxdiv_offset,u8 mux_shift,u8 mux_width,u8 mux_flags,u32 * mux_table,int div_offset,u8 div_shift,u8 div_width,u8 div_flags,struct clk_div_table * div_table,int gate_offset,u8 gate_shift,u8 gate_flags,unsigned long flags,spinlock_t * lock)37 static struct clk *rockchip_clk_register_branch(const char *name,
38 const char *const *parent_names, u8 num_parents,
39 void __iomem *base,
40 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
41 u32 *mux_table,
42 int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
43 struct clk_div_table *div_table, int gate_offset,
44 u8 gate_shift, u8 gate_flags, unsigned long flags,
45 spinlock_t *lock)
46 {
47 struct clk_hw *hw;
48 struct clk_mux *mux = NULL;
49 struct clk_gate *gate = NULL;
50 struct clk_divider *div = NULL;
51 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
52 *gate_ops = NULL;
53 int ret;
54
55 if (num_parents > 1) {
56 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
57 if (!mux)
58 return ERR_PTR(-ENOMEM);
59
60 mux->reg = base + muxdiv_offset;
61 mux->shift = mux_shift;
62 mux->mask = BIT(mux_width) - 1;
63 mux->flags = mux_flags;
64 mux->table = mux_table;
65 mux->lock = lock;
66 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
67 : &clk_mux_ops;
68 }
69
70 if (gate_offset >= 0) {
71 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
72 if (!gate) {
73 ret = -ENOMEM;
74 goto err_gate;
75 }
76
77 gate->flags = gate_flags;
78 gate->reg = base + gate_offset;
79 gate->bit_idx = gate_shift;
80 gate->lock = lock;
81 gate_ops = &clk_gate_ops;
82 }
83
84 if (div_width > 0) {
85 div = kzalloc(sizeof(*div), GFP_KERNEL);
86 if (!div) {
87 ret = -ENOMEM;
88 goto err_div;
89 }
90
91 div->flags = div_flags;
92 if (div_offset)
93 div->reg = base + div_offset;
94 else
95 div->reg = base + muxdiv_offset;
96 div->shift = div_shift;
97 div->width = div_width;
98 div->lock = lock;
99 div->table = div_table;
100 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
101 ? &clk_divider_ro_ops
102 : &clk_divider_ops;
103 }
104
105 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
106 mux ? &mux->hw : NULL, mux_ops,
107 div ? &div->hw : NULL, div_ops,
108 gate ? &gate->hw : NULL, gate_ops,
109 flags);
110 if (IS_ERR(hw)) {
111 kfree(div);
112 kfree(gate);
113 return ERR_CAST(hw);
114 }
115
116 return hw->clk;
117 err_div:
118 kfree(gate);
119 err_gate:
120 kfree(mux);
121 return ERR_PTR(ret);
122 }
123
124 struct rockchip_clk_frac {
125 struct notifier_block clk_nb;
126 struct clk_fractional_divider div;
127 struct clk_gate gate;
128
129 struct clk_mux mux;
130 const struct clk_ops *mux_ops;
131 int mux_frac_idx;
132
133 bool rate_change_remuxed;
134 int rate_change_idx;
135 };
136
137 #define to_rockchip_clk_frac_nb(nb) \
138 container_of(nb, struct rockchip_clk_frac, clk_nb)
139
rockchip_clk_frac_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)140 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
141 unsigned long event, void *data)
142 {
143 struct clk_notifier_data *ndata = data;
144 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
145 struct clk_mux *frac_mux = &frac->mux;
146 int ret = 0;
147
148 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
149 __func__, event, ndata->old_rate, ndata->new_rate);
150 if (event == PRE_RATE_CHANGE) {
151 frac->rate_change_idx =
152 frac->mux_ops->get_parent(&frac_mux->hw);
153 if (frac->rate_change_idx != frac->mux_frac_idx) {
154 frac->mux_ops->set_parent(&frac_mux->hw,
155 frac->mux_frac_idx);
156 frac->rate_change_remuxed = 1;
157 }
158 } else if (event == POST_RATE_CHANGE) {
159 /*
160 * The POST_RATE_CHANGE notifier runs directly after the
161 * divider clock is set in clk_change_rate, so we'll have
162 * remuxed back to the original parent before clk_change_rate
163 * reaches the mux itself.
164 */
165 if (frac->rate_change_remuxed) {
166 frac->mux_ops->set_parent(&frac_mux->hw,
167 frac->rate_change_idx);
168 frac->rate_change_remuxed = 0;
169 }
170 }
171
172 return notifier_from_errno(ret);
173 }
174
175 /**
176 * fractional divider must set that denominator is 20 times larger than
177 * numerator to generate precise clock frequency.
178 */
rockchip_fractional_approximation(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate,unsigned long * m,unsigned long * n)179 static void rockchip_fractional_approximation(struct clk_hw *hw,
180 unsigned long rate, unsigned long *parent_rate,
181 unsigned long *m, unsigned long *n)
182 {
183 struct clk_fractional_divider *fd = to_clk_fd(hw);
184 unsigned long p_rate, p_parent_rate;
185 struct clk_hw *p_parent;
186 unsigned long scale;
187
188 p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
189 if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
190 p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
191 if (!p_parent) {
192 *parent_rate = p_rate;
193 } else {
194 p_parent_rate = clk_hw_get_rate(p_parent);
195 *parent_rate = p_parent_rate;
196 }
197
198 if (*parent_rate < rate * 20) {
199 /*
200 * Fractional frequency divider to do
201 * integer frequency divider does not
202 * need 20 times the limit.
203 */
204 if (!(*parent_rate % rate)) {
205 *m = 1;
206 *n = *parent_rate / rate;
207 return;
208 } else if (!(fd->flags & CLK_FRAC_DIVIDER_NO_LIMIT)) {
209 pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
210 clk_hw_get_name(hw),
211 *parent_rate, rate);
212 *m = 0;
213 *n = 1;
214 return;
215 }
216 }
217 }
218
219 /*
220 * Get rate closer to *parent_rate to guarantee there is no overflow
221 * for m and n. In the result it will be the nearest rate left shifted
222 * by (scale - fd->nwidth) bits.
223 */
224 scale = fls_long(*parent_rate / rate - 1);
225 if (scale > fd->nwidth)
226 rate <<= scale - fd->nwidth;
227
228 rational_best_approximation(rate, *parent_rate,
229 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
230 m, n);
231 }
232
rockchip_clk_register_frac_branch(struct rockchip_clk_provider * ctx,const char * name,const char * const * parent_names,u8 num_parents,void __iomem * base,int muxdiv_offset,u8 div_flags,int gate_offset,u8 gate_shift,u8 gate_flags,unsigned long flags,struct rockchip_clk_branch * child,spinlock_t * lock)233 static struct clk *rockchip_clk_register_frac_branch(
234 struct rockchip_clk_provider *ctx, const char *name,
235 const char *const *parent_names, u8 num_parents,
236 void __iomem *base, int muxdiv_offset, u8 div_flags,
237 int gate_offset, u8 gate_shift, u8 gate_flags,
238 unsigned long flags, struct rockchip_clk_branch *child,
239 spinlock_t *lock)
240 {
241 struct clk_hw *hw;
242 struct rockchip_clk_frac *frac;
243 struct clk_gate *gate = NULL;
244 struct clk_fractional_divider *div = NULL;
245 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
246
247 if (muxdiv_offset < 0)
248 return ERR_PTR(-EINVAL);
249
250 if (child && child->branch_type != branch_mux) {
251 pr_err("%s: fractional child clock for %s can only be a mux\n",
252 __func__, name);
253 return ERR_PTR(-EINVAL);
254 }
255
256 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
257 if (!frac)
258 return ERR_PTR(-ENOMEM);
259
260 if (gate_offset >= 0) {
261 gate = &frac->gate;
262 gate->flags = gate_flags;
263 gate->reg = base + gate_offset;
264 gate->bit_idx = gate_shift;
265 gate->lock = lock;
266 gate_ops = &clk_gate_ops;
267 }
268
269 div = &frac->div;
270 div->flags = div_flags;
271 div->reg = base + muxdiv_offset;
272 div->mshift = 16;
273 div->mwidth = 16;
274 div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
275 div->nshift = 0;
276 div->nwidth = 16;
277 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
278 div->lock = lock;
279 div->approximation = rockchip_fractional_approximation;
280 div_ops = &clk_fractional_divider_ops;
281
282 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
283 NULL, NULL,
284 &div->hw, div_ops,
285 gate ? &gate->hw : NULL, gate_ops,
286 flags | CLK_SET_RATE_UNGATE);
287 if (IS_ERR(hw)) {
288 kfree(frac);
289 return ERR_CAST(hw);
290 }
291
292 if (child) {
293 struct clk_mux *frac_mux = &frac->mux;
294 struct clk_init_data init;
295 struct clk *mux_clk;
296 int ret;
297
298 frac->mux_frac_idx = match_string(child->parent_names,
299 child->num_parents, name);
300 frac->mux_ops = &clk_mux_ops;
301 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
302
303 frac_mux->reg = base + child->muxdiv_offset;
304 frac_mux->shift = child->mux_shift;
305 frac_mux->mask = BIT(child->mux_width) - 1;
306 frac_mux->flags = child->mux_flags;
307 if (child->mux_table)
308 frac_mux->table = child->mux_table;
309 frac_mux->lock = lock;
310 frac_mux->hw.init = &init;
311
312 init.name = child->name;
313 init.flags = child->flags | CLK_SET_RATE_PARENT;
314 init.ops = frac->mux_ops;
315 init.parent_names = child->parent_names;
316 init.num_parents = child->num_parents;
317
318 mux_clk = clk_register(NULL, &frac_mux->hw);
319 if (IS_ERR(mux_clk)) {
320 kfree(frac);
321 return mux_clk;
322 }
323
324 rockchip_clk_add_lookup(ctx, mux_clk, child->id);
325
326 /* notifier on the fraction divider to catch rate changes */
327 if (frac->mux_frac_idx >= 0) {
328 pr_debug("%s: found fractional parent in mux at pos %d\n",
329 __func__, frac->mux_frac_idx);
330 ret = clk_notifier_register(hw->clk, &frac->clk_nb);
331 if (ret)
332 pr_err("%s: failed to register clock notifier for %s\n",
333 __func__, name);
334 } else {
335 pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
336 __func__, name, child->name);
337 }
338 }
339
340 return hw->clk;
341 }
342
rockchip_clk_register_factor_branch(const char * name,const char * const * parent_names,u8 num_parents,void __iomem * base,unsigned int mult,unsigned int div,int gate_offset,u8 gate_shift,u8 gate_flags,unsigned long flags,spinlock_t * lock)343 static struct clk *rockchip_clk_register_factor_branch(const char *name,
344 const char *const *parent_names, u8 num_parents,
345 void __iomem *base, unsigned int mult, unsigned int div,
346 int gate_offset, u8 gate_shift, u8 gate_flags,
347 unsigned long flags, spinlock_t *lock)
348 {
349 struct clk_hw *hw;
350 struct clk_gate *gate = NULL;
351 struct clk_fixed_factor *fix = NULL;
352
353 /* without gate, register a simple factor clock */
354 if (gate_offset == 0) {
355 return clk_register_fixed_factor(NULL, name,
356 parent_names[0], flags, mult,
357 div);
358 }
359
360 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
361 if (!gate)
362 return ERR_PTR(-ENOMEM);
363
364 gate->flags = gate_flags;
365 gate->reg = base + gate_offset;
366 gate->bit_idx = gate_shift;
367 gate->lock = lock;
368
369 fix = kzalloc(sizeof(*fix), GFP_KERNEL);
370 if (!fix) {
371 kfree(gate);
372 return ERR_PTR(-ENOMEM);
373 }
374
375 fix->mult = mult;
376 fix->div = div;
377
378 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
379 NULL, NULL,
380 &fix->hw, &clk_fixed_factor_ops,
381 &gate->hw, &clk_gate_ops, flags);
382 if (IS_ERR(hw)) {
383 kfree(fix);
384 kfree(gate);
385 return ERR_CAST(hw);
386 }
387
388 return hw->clk;
389 }
390
rockchip_clk_init(struct device_node * np,void __iomem * base,unsigned long nr_clks)391 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
392 void __iomem *base,
393 unsigned long nr_clks)
394 {
395 struct rockchip_clk_provider *ctx;
396 struct clk **clk_table;
397 int i;
398
399 ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
400 if (!ctx)
401 return ERR_PTR(-ENOMEM);
402
403 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
404 if (!clk_table)
405 goto err_free;
406
407 for (i = 0; i < nr_clks; ++i)
408 clk_table[i] = ERR_PTR(-ENOENT);
409
410 ctx->reg_base = base;
411 ctx->clk_data.clks = clk_table;
412 ctx->clk_data.clk_num = nr_clks;
413 ctx->cru_node = np;
414 spin_lock_init(&ctx->lock);
415
416 ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
417 "rockchip,grf");
418 ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
419 "rockchip,pmugrf");
420
421 return ctx;
422
423 err_free:
424 kfree(ctx);
425 return ERR_PTR(-ENOMEM);
426 }
427 EXPORT_SYMBOL_GPL(rockchip_clk_init);
428
rockchip_clk_of_add_provider(struct device_node * np,struct rockchip_clk_provider * ctx)429 void rockchip_clk_of_add_provider(struct device_node *np,
430 struct rockchip_clk_provider *ctx)
431 {
432 if (of_clk_add_provider(np, of_clk_src_onecell_get,
433 &ctx->clk_data))
434 pr_err("%s: could not register clk provider\n", __func__);
435 }
436 EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
437
rockchip_clk_add_lookup(struct rockchip_clk_provider * ctx,struct clk * clk,unsigned int id)438 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
439 struct clk *clk, unsigned int id)
440 {
441 if (ctx->clk_data.clks && id)
442 ctx->clk_data.clks[id] = clk;
443 }
444 EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
445
rockchip_clk_register_plls(struct rockchip_clk_provider * ctx,struct rockchip_pll_clock * list,unsigned int nr_pll,int grf_lock_offset)446 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
447 struct rockchip_pll_clock *list,
448 unsigned int nr_pll, int grf_lock_offset)
449 {
450 struct clk *clk;
451 int idx;
452
453 for (idx = 0; idx < nr_pll; idx++, list++) {
454 clk = rockchip_clk_register_pll(ctx, list->type, list->name,
455 list->parent_names, list->num_parents,
456 list->con_offset, grf_lock_offset,
457 list->lock_shift, list->mode_offset,
458 list->mode_shift, list->rate_table,
459 list->flags, list->pll_flags);
460 if (IS_ERR(clk)) {
461 pr_err("%s: failed to register clock %s\n", __func__,
462 list->name);
463 continue;
464 }
465
466 rockchip_clk_add_lookup(ctx, clk, list->id);
467 }
468 }
469 EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
470
rockchip_clk_register_branches(struct rockchip_clk_provider * ctx,struct rockchip_clk_branch * list,unsigned int nr_clk)471 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
472 struct rockchip_clk_branch *list,
473 unsigned int nr_clk)
474 {
475 struct clk *clk = NULL;
476 unsigned int idx;
477 unsigned long flags;
478
479 for (idx = 0; idx < nr_clk; idx++, list++) {
480 flags = list->flags;
481
482 /* catch simple muxes */
483 switch (list->branch_type) {
484 case branch_mux:
485 if (list->mux_table)
486 clk = clk_register_mux_table(NULL, list->name,
487 list->parent_names, list->num_parents,
488 flags,
489 ctx->reg_base + list->muxdiv_offset,
490 list->mux_shift,
491 BIT(list->mux_width) - 1,
492 list->mux_flags, list->mux_table,
493 &ctx->lock);
494 else
495 clk = clk_register_mux(NULL, list->name,
496 list->parent_names, list->num_parents,
497 flags,
498 ctx->reg_base + list->muxdiv_offset,
499 list->mux_shift, list->mux_width,
500 list->mux_flags, &ctx->lock);
501 break;
502 case branch_muxgrf:
503 clk = rockchip_clk_register_muxgrf(list->name,
504 list->parent_names, list->num_parents,
505 flags, ctx->grf, list->muxdiv_offset,
506 list->mux_shift, list->mux_width,
507 list->mux_flags);
508 break;
509 case branch_muxpmugrf:
510 clk = rockchip_clk_register_muxgrf(list->name,
511 list->parent_names, list->num_parents,
512 flags, ctx->pmugrf, list->muxdiv_offset,
513 list->mux_shift, list->mux_width,
514 list->mux_flags);
515 break;
516 case branch_divider:
517 if (list->div_table)
518 clk = clk_register_divider_table(NULL,
519 list->name, list->parent_names[0],
520 flags,
521 ctx->reg_base + list->muxdiv_offset,
522 list->div_shift, list->div_width,
523 list->div_flags, list->div_table,
524 &ctx->lock);
525 else
526 clk = clk_register_divider(NULL, list->name,
527 list->parent_names[0], flags,
528 ctx->reg_base + list->muxdiv_offset,
529 list->div_shift, list->div_width,
530 list->div_flags, &ctx->lock);
531 break;
532 case branch_fraction_divider:
533 clk = rockchip_clk_register_frac_branch(ctx, list->name,
534 list->parent_names, list->num_parents,
535 ctx->reg_base, list->muxdiv_offset,
536 list->div_flags,
537 list->gate_offset, list->gate_shift,
538 list->gate_flags, flags, list->child,
539 &ctx->lock);
540 break;
541 case branch_half_divider:
542 clk = rockchip_clk_register_halfdiv(list->name,
543 list->parent_names, list->num_parents,
544 ctx->reg_base, list->muxdiv_offset,
545 list->mux_shift, list->mux_width,
546 list->mux_flags, list->div_offset,
547 list->div_shift, list->div_width,
548 list->div_flags, list->gate_offset,
549 list->gate_shift, list->gate_flags,
550 flags, &ctx->lock);
551 break;
552 case branch_gate:
553 flags |= CLK_SET_RATE_PARENT;
554
555 clk = clk_register_gate(NULL, list->name,
556 list->parent_names[0], flags,
557 ctx->reg_base + list->gate_offset,
558 list->gate_shift, list->gate_flags, &ctx->lock);
559 break;
560 case branch_gate_no_set_rate:
561 flags &= ~CLK_SET_RATE_PARENT;
562
563 clk = clk_register_gate(NULL, list->name,
564 list->parent_names[0], flags,
565 ctx->reg_base + list->gate_offset,
566 list->gate_shift, list->gate_flags, &ctx->lock);
567 break;
568 case branch_composite:
569 clk = rockchip_clk_register_branch(list->name,
570 list->parent_names, list->num_parents,
571 ctx->reg_base, list->muxdiv_offset,
572 list->mux_shift,
573 list->mux_width, list->mux_flags,
574 list->mux_table, list->div_offset,
575 list->div_shift, list->div_width,
576 list->div_flags, list->div_table,
577 list->gate_offset, list->gate_shift,
578 list->gate_flags, flags, &ctx->lock);
579 break;
580 case branch_mmc:
581 clk = rockchip_clk_register_mmc(
582 list->name,
583 list->parent_names, list->num_parents,
584 ctx->reg_base + list->muxdiv_offset,
585 list->div_shift
586 );
587 break;
588 case branch_inverter:
589 #ifdef CONFIG_ROCKCHIP_CLK_INV
590 clk = rockchip_clk_register_inverter(
591 list->name, list->parent_names,
592 list->num_parents,
593 ctx->reg_base + list->muxdiv_offset,
594 list->div_shift, list->div_flags, &ctx->lock);
595 #endif
596 break;
597 case branch_factor:
598 clk = rockchip_clk_register_factor_branch(
599 list->name, list->parent_names,
600 list->num_parents, ctx->reg_base,
601 list->div_shift, list->div_width,
602 list->gate_offset, list->gate_shift,
603 list->gate_flags, flags, &ctx->lock);
604 break;
605 case branch_ddrclk:
606 clk = rockchip_clk_register_ddrclk(
607 list->name, list->flags,
608 list->parent_names, list->num_parents,
609 list->muxdiv_offset, list->mux_shift,
610 list->mux_width, list->div_shift,
611 list->div_width, list->div_flags,
612 ctx->reg_base);
613 break;
614 }
615
616 /* none of the cases above matched */
617 if (!clk) {
618 pr_err("%s: unknown clock type %d\n",
619 __func__, list->branch_type);
620 continue;
621 }
622
623 if (IS_ERR(clk)) {
624 pr_err("%s: failed to register clock %s: %ld\n",
625 __func__, list->name, PTR_ERR(clk));
626 continue;
627 }
628
629 rockchip_clk_add_lookup(ctx, clk, list->id);
630 }
631 }
632 EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
633
rockchip_clk_register_armclk(struct rockchip_clk_provider * ctx,unsigned int lookup_id,const char * name,u8 num_parents,struct clk * parent,struct clk * alt_parent,const struct rockchip_cpuclk_reg_data * reg_data,const struct rockchip_cpuclk_rate_table * rates,int nrates)634 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
635 unsigned int lookup_id,
636 const char *name,
637 u8 num_parents,
638 struct clk *parent, struct clk *alt_parent,
639 const struct rockchip_cpuclk_reg_data *reg_data,
640 const struct rockchip_cpuclk_rate_table *rates,
641 int nrates)
642 {
643 struct clk *clk;
644
645 clk = rockchip_clk_register_cpuclk(name, num_parents,
646 parent, alt_parent,
647 reg_data, rates, nrates,
648 ctx->reg_base, &ctx->lock);
649 if (IS_ERR(clk)) {
650 pr_err("%s: failed to register clock %s: %ld\n",
651 __func__, name, PTR_ERR(clk));
652 return;
653 }
654
655 rockchip_clk_add_lookup(ctx, clk, lookup_id);
656 }
657 EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
658
rockchip_clk_register_armclk_v2(struct rockchip_clk_provider * ctx,struct rockchip_clk_branch * list,const struct rockchip_cpuclk_rate_table * rates,int nrates)659 void rockchip_clk_register_armclk_v2(struct rockchip_clk_provider *ctx,
660 struct rockchip_clk_branch *list,
661 const struct rockchip_cpuclk_rate_table *rates,
662 int nrates)
663 {
664 struct clk *clk;
665
666 clk = rockchip_clk_register_cpuclk_v2(list->name, list->parent_names,
667 list->num_parents, ctx->reg_base,
668 list->muxdiv_offset, list->mux_shift,
669 list->mux_width, list->mux_flags,
670 list->div_offset, list->div_shift,
671 list->div_width, list->div_flags,
672 list->flags, &ctx->lock, rates, nrates);
673 if (IS_ERR(clk)) {
674 pr_err("%s: failed to register clock %s: %ld\n",
675 __func__, list->name, PTR_ERR(clk));
676 return;
677 }
678
679 rockchip_clk_add_lookup(ctx, clk, list->id);
680 }
681 EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk_v2);
682
683 void (*rk_dump_cru)(void);
684 EXPORT_SYMBOL(rk_dump_cru);
685
rk_clk_panic(struct notifier_block * this,unsigned long ev,void * ptr)686 static int rk_clk_panic(struct notifier_block *this,
687 unsigned long ev, void *ptr)
688 {
689 if (rk_dump_cru)
690 rk_dump_cru();
691 return NOTIFY_DONE;
692 }
693
694 static struct notifier_block rk_clk_panic_block = {
695 .notifier_call = rk_clk_panic,
696 };
697
698 static void __iomem *rst_base;
699 static unsigned int reg_restart;
700 static void (*cb_restart)(void);
rockchip_restart_notify(struct notifier_block * this,unsigned long mode,void * cmd)701 static int rockchip_restart_notify(struct notifier_block *this,
702 unsigned long mode, void *cmd)
703 {
704 if (cb_restart)
705 cb_restart();
706
707 writel(0xfdb9, rst_base + reg_restart);
708 return NOTIFY_DONE;
709 }
710
711 static struct notifier_block rockchip_restart_handler = {
712 .notifier_call = rockchip_restart_notify,
713 .priority = 128,
714 };
715
716 void
rockchip_register_restart_notifier(struct rockchip_clk_provider * ctx,unsigned int reg,void (* cb)(void))717 rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
718 unsigned int reg,
719 void (*cb)(void))
720 {
721 int ret;
722
723 rst_base = ctx->reg_base;
724 reg_restart = reg;
725 cb_restart = cb;
726 ret = register_restart_handler(&rockchip_restart_handler);
727 if (ret)
728 pr_err("%s: cannot register restart handler, %d\n",
729 __func__, ret);
730 atomic_notifier_chain_register(&panic_notifier_list,
731 &rk_clk_panic_block);
732 }
733 EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);
734
735 #ifdef MODULE
736 static struct clk **protect_clocks;
737 static unsigned int protect_nclocks;
738
rockchip_clk_protect(struct rockchip_clk_provider * ctx,unsigned int * clocks,unsigned int nclocks)739 int rockchip_clk_protect(struct rockchip_clk_provider *ctx,
740 unsigned int *clocks, unsigned int nclocks)
741 {
742 struct clk *clk = NULL;
743 int i = 0;
744
745 if (protect_clocks || !ctx || !clocks || !ctx->clk_data.clks)
746 return 0;
747
748 protect_clocks = kcalloc(nclocks, sizeof(void *), GFP_KERNEL);
749 if (!protect_clocks)
750 return -ENOMEM;
751
752 for (i = 0; i < nclocks; i++) {
753 if (clocks[i] >= ctx->clk_data.clk_num) {
754 pr_err("%s: invalid clock id %u\n", __func__, clocks[i]);
755 continue;
756 }
757 clk = ctx->clk_data.clks[clocks[i]];
758 if (clk) {
759 clk_prepare_enable(clk);
760 protect_clocks[i] = clk;
761 }
762 }
763 protect_nclocks = nclocks;
764
765 return 0;
766 }
767 EXPORT_SYMBOL_GPL(rockchip_clk_protect);
768
rockchip_clk_unprotect(void)769 void rockchip_clk_unprotect(void)
770 {
771 int i = 0;
772
773 if (!protect_clocks || !protect_nclocks)
774 return;
775
776 for (i = 0; i < protect_nclocks; i++) {
777 if (protect_clocks[i])
778 clk_disable_unprepare(protect_clocks[i]);
779 }
780 protect_nclocks = 0;
781 kfree(protect_clocks);
782 protect_clocks = NULL;
783
784 }
785 EXPORT_SYMBOL_GPL(rockchip_clk_unprotect);
786 #endif /* MODULE */
787