1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
8 *
9 * based on
10 *
11 * samsung/clk.h
12 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
13 * Copyright (c) 2013 Linaro Ltd.
14 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 */
16
17 #ifndef CLK_ROCKCHIP_CLK_H
18 #define CLK_ROCKCHIP_CLK_H
19
20 #include <linux/io.h>
21 #include <linux/clk-provider.h>
22
23 struct clk;
24
25 #define HIWORD_UPDATE(val, mask, shift) \
26 ((val) << (shift) | (mask) << ((shift) + 16))
27
28 /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
40 #define BOOST_PLL_CON_MASK 0xffff
41 #define BOOST_CORE_DIV_MASK 0x1f
42 #define BOOST_CORE_DIV_SHIFT 0
43 #define BOOST_BACKUP_PLL_MASK 0x3
44 #define BOOST_BACKUP_PLL_SHIFT 8
45 #define BOOST_BACKUP_PLL_USAGE_MASK 0x1
46 #define BOOST_BACKUP_PLL_USAGE_SHIFT 12
47 #define BOOST_BACKUP_PLL_USAGE_BORROW 0
48 #define BOOST_BACKUP_PLL_USAGE_TARGET 1
49 #define BOOST_ENABLE_MASK 0x1
50 #define BOOST_ENABLE_SHIFT 0
51 #define BOOST_RECOVERY_MASK 0x1
52 #define BOOST_RECOVERY_SHIFT 1
53 #define BOOST_SW_CTRL_MASK 0x1
54 #define BOOST_SW_CTRL_SHIFT 2
55 #define BOOST_LOW_FREQ_EN_MASK 0x1
56 #define BOOST_LOW_FREQ_EN_SHIFT 3
57 #define BOOST_STATIS_ENABLE_MASK 0x1
58 #define BOOST_STATIS_ENABLE_SHIFT 4
59 #define BOOST_BUSY_STATE BIT(8)
60
61 #define PX30_PLL_CON(x) ((x) * 0x4)
62 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
63 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
64 #define PX30_GLB_SRST_FST 0xb8
65 #define PX30_GLB_SRST_SND 0xbc
66 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
67 #define PX30_MODE_CON 0xa0
68 #define PX30_MISC_CON 0xa4
69 #define PX30_SDMMC_CON0 0x380
70 #define PX30_SDMMC_CON1 0x384
71 #define PX30_SDIO_CON0 0x388
72 #define PX30_SDIO_CON1 0x38c
73 #define PX30_EMMC_CON0 0x390
74 #define PX30_EMMC_CON1 0x394
75
76 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
77 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
78 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
79 #define PX30_PMU_MODE 0x0020
80
81 #define RV1106_TOPCRU_BASE 0x10000
82 #define RV1106_PERICRU_BASE 0x12000
83 #define RV1106_VICRU_BASE 0x14000
84 #define RV1106_NPUCRU_BASE 0x16000
85 #define RV1106_CORECRU_BASE 0x18000
86 #define RV1106_VEPUCRU_BASE 0x1A000
87 #define RV1106_VOCRU_BASE 0x1C000
88 #define RV1106_DDRCRU_BASE 0x1E000
89 #define RV1106_SUBDDRCRU_BASE 0x1F000
90
91 #define RV1106_VI_GRF_BASE 0x50000
92 #define RV1106_VO_GRF_BASE 0x60000
93
94 #define RV1106_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300)
95 #define RV1106_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800)
96 #define RV1106_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00)
97 #define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE)
98 #define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE)
99 #define RV1106_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
100 #define RV1106_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
101 #define RV1106_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_TOPCRU_BASE)
102 #define RV1106_GLB_SRST_FST (0xc08 + RV1106_TOPCRU_BASE)
103 #define RV1106_GLB_SRST_SND (0xc0c + RV1106_TOPCRU_BASE)
104 #define RV1106_SDIO_CON0 (0x1c + RV1106_VO_GRF_BASE)
105 #define RV1106_SDIO_CON1 (0x20 + RV1106_VO_GRF_BASE)
106 #define RV1106_SDMMC_CON0 (0x4 + RV1106_VI_GRF_BASE)
107 #define RV1106_SDMMC_CON1 (0x8 + RV1106_VI_GRF_BASE)
108 #define RV1106_EMMC_CON0 (0x20)
109 #define RV1106_EMMC_CON1 (0x24)
110 #define RV1106_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
111 #define RV1106_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
112 #define RV1106_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_PERICRU_BASE)
113 #define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
114 #define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
115 #define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
116 #define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
117 #define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
118 #define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
119 #define RV1106_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
120 #define RV1106_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
121 #define RV1106_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_NPUCRU_BASE)
122 #define RV1106_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
123 #define RV1106_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
124 #define RV1106_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_CORECRU_BASE)
125 #define RV1106_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
126 #define RV1106_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
127 #define RV1106_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VEPUCRU_BASE)
128 #define RV1106_VOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
129 #define RV1106_VOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
130 #define RV1106_VOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VOCRU_BASE)
131 #define RV1106_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
132 #define RV1106_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
133 #define RV1106_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_DDRCRU_BASE)
134 #define RV1106_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
135 #define RV1106_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
136 #define RV1106_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_SUBDDRCRU_BASE)
137 #define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE)
138
139 #define RV1108_PLL_CON(x) ((x) * 0x4)
140 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
141 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
142 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
143 #define RV1108_GLB_SRST_FST 0x1c0
144 #define RV1108_GLB_SRST_SND 0x1c4
145 #define RV1108_MISC_CON 0x1cc
146 #define RV1108_SDMMC_CON0 0x1d8
147 #define RV1108_SDMMC_CON1 0x1dc
148 #define RV1108_SDIO_CON0 0x1e0
149 #define RV1108_SDIO_CON1 0x1e4
150 #define RV1108_EMMC_CON0 0x1e8
151 #define RV1108_EMMC_CON1 0x1ec
152
153 #define RV1126_PMU_MODE 0x0
154 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
155 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
156 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
157 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
158 #define RV1126_PLL_CON(x) ((x) * 0x4)
159 #define RV1126_MODE_CON 0x90
160 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
161 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
162 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
163 #define RV1126_GLB_SRST_FST 0x408
164 #define RV1126_GLB_SRST_SND 0x40c
165 #define RV1126_SDMMC_CON0 0x440
166 #define RV1126_SDMMC_CON1 0x444
167 #define RV1126_SDIO_CON0 0x448
168 #define RV1126_SDIO_CON1 0x44c
169 #define RV1126_EMMC_CON0 0x450
170 #define RV1126_EMMC_CON1 0x454
171
172 /*
173 * register positions shared by RK1808 RK2928, RK3036,
174 * RK3066, RK3188 and RK3228
175 */
176
177 #define RK1808_PLL_CON(x) ((x) * 0x4)
178 #define RK1808_MODE_CON 0xa0
179 #define RK1808_MISC_CON 0xa4
180 #define RK1808_MISC1_CON 0xa8
181 #define RK1808_GLB_SRST_FST 0xb8
182 #define RK1808_GLB_SRST_SND 0xbc
183 #define RK1808_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
184 #define RK1808_CLKGATE_CON(x) ((x) * 0x4 + 0x230)
185 #define RK1808_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
186 #define RK1808_SDMMC_CON0 0x380
187 #define RK1808_SDMMC_CON1 0x384
188 #define RK1808_SDIO_CON0 0x388
189 #define RK1808_SDIO_CON1 0x38c
190 #define RK1808_EMMC_CON0 0x390
191 #define RK1808_EMMC_CON1 0x394
192
193 #define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000)
194 #define RK1808_PMU_MODE_CON 0x4020
195 #define RK1808_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x4040)
196 #define RK1808_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x4080)
197
198 #define RK2928_PLL_CON(x) ((x) * 0x4)
199 #define RK2928_MODE_CON 0x40
200 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
201 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
202 #define RK2928_GLB_SRST_FST 0x100
203 #define RK2928_GLB_SRST_SND 0x104
204 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
205 #define RK2928_MISC_CON 0x134
206
207 #define RK3036_SDMMC_CON0 0x144
208 #define RK3036_SDMMC_CON1 0x148
209 #define RK3036_SDIO_CON0 0x14c
210 #define RK3036_SDIO_CON1 0x150
211 #define RK3036_EMMC_CON0 0x154
212 #define RK3036_EMMC_CON1 0x158
213
214 #define RK3228_GLB_SRST_FST 0x1f0
215 #define RK3228_GLB_SRST_SND 0x1f4
216 #define RK3228_SDMMC_CON0 0x1c0
217 #define RK3228_SDMMC_CON1 0x1c4
218 #define RK3228_SDIO_CON0 0x1c8
219 #define RK3228_SDIO_CON1 0x1cc
220 #define RK3228_EMMC_CON0 0x1d8
221 #define RK3228_EMMC_CON1 0x1dc
222
223 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
224 #define RK3288_MODE_CON 0x50
225 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
226 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
227 #define RK3288_GLB_SRST_FST 0x1b0
228 #define RK3288_GLB_SRST_SND 0x1b4
229 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
230 #define RK3288_MISC_CON 0x1e8
231 #define RK3288_SDMMC_CON0 0x200
232 #define RK3288_SDMMC_CON1 0x204
233 #define RK3288_SDIO0_CON0 0x208
234 #define RK3288_SDIO0_CON1 0x20c
235 #define RK3288_SDIO1_CON0 0x210
236 #define RK3288_SDIO1_CON1 0x214
237 #define RK3288_EMMC_CON0 0x218
238 #define RK3288_EMMC_CON1 0x21c
239
240 #define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
241 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
242 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
243 #define RK3308_GLB_SRST_FST 0xb8
244 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
245 #define RK3308_MODE_CON 0xa0
246 #define RK3308_SDMMC_CON0 0x480
247 #define RK3308_SDMMC_CON1 0x484
248 #define RK3308_SDIO_CON0 0x488
249 #define RK3308_SDIO_CON1 0x48c
250 #define RK3308_EMMC_CON0 0x490
251 #define RK3308_EMMC_CON1 0x494
252
253 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
254 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
255 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
256 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
257 #define RK3328_GLB_SRST_FST 0x9c
258 #define RK3328_GLB_SRST_SND 0x98
259 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
260 #define RK3328_MODE_CON 0x80
261 #define RK3328_MISC_CON 0x84
262 #define RK3328_SDMMC_CON0 0x380
263 #define RK3328_SDMMC_CON1 0x384
264 #define RK3328_SDIO_CON0 0x388
265 #define RK3328_SDIO_CON1 0x38c
266 #define RK3328_EMMC_CON0 0x390
267 #define RK3328_EMMC_CON1 0x394
268 #define RK3328_SDMMC_EXT_CON0 0x398
269 #define RK3328_SDMMC_EXT_CON1 0x39C
270
271 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
272 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
273 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
274 #define RK3368_GLB_SRST_FST 0x280
275 #define RK3368_GLB_SRST_SND 0x284
276 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
277 #define RK3368_MISC_CON 0x380
278 #define RK3368_SDMMC_CON0 0x400
279 #define RK3368_SDMMC_CON1 0x404
280 #define RK3368_SDIO0_CON0 0x408
281 #define RK3368_SDIO0_CON1 0x40c
282 #define RK3368_SDIO1_CON0 0x410
283 #define RK3368_SDIO1_CON1 0x414
284 #define RK3368_EMMC_CON0 0x418
285 #define RK3368_EMMC_CON1 0x41c
286
287 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
288 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
289 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
290 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
291 #define RK3399_GLB_SRST_FST 0x500
292 #define RK3399_GLB_SRST_SND 0x504
293 #define RK3399_GLB_CNT_TH 0x508
294 #define RK3399_MISC_CON 0x50c
295 #define RK3399_RST_CON 0x510
296 #define RK3399_RST_ST 0x514
297 #define RK3399_SDMMC_CON0 0x580
298 #define RK3399_SDMMC_CON1 0x584
299 #define RK3399_SDIO_CON0 0x588
300 #define RK3399_SDIO_CON1 0x58c
301
302 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
303 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
304 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
305 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
306
307 #define RK3528_PMU_CRU_BASE 0x10000
308 #define RK3528_PCIE_CRU_BASE 0x20000
309 #define RK3528_DDRPHY_CRU_BASE 0x28000
310 #define RK3528_VPU_GRF_BASE 0x40000
311 #define RK3528_VO_GRF_BASE 0x60000
312 #define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24)
313 #define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28)
314 #define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4)
315 #define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8)
316 #define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc)
317 #define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10)
318 #define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
319 #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
320 #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
321 #define RK3528_MODE_CON 0x280
322 #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
323 #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
324 #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
325 #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
326 #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
327 #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
328 #define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
329 #define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
330 #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
331 #define RK3528_GLB_CNT_TH 0xc00
332 #define RK3528_GLB_SRST_FST 0xc08
333 #define RK3528_GLB_SRST_SND 0xc0c
334
335 #define RK3562_PMU0_CRU_BASE 0x10000
336 #define RK3562_PMU1_CRU_BASE 0x18000
337 #define RK3562_DDR_CRU_BASE 0x20000
338 #define RK3562_SUBDDR_CRU_BASE 0x28000
339 #define RK3562_PERI_CRU_BASE 0x30000
340
341 #define RK3562_PLL_CON(x) RK2928_PLL_CON(x)
342 #define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
343 #define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
344 #define RK3562_MODE_CON 0x600
345 #define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
346 #define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
347 #define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
348 #define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
349 #define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
350 #define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
351 #define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
352 #define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
353 #define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
354 #define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
355 #define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
356 #define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
357 #define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
358 #define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
359 #define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
360 #define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
361 #define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
362 #define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
363 #define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
364 #define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
365 #define RK3562_GLB_SRST_FST 0x614
366 #define RK3562_GLB_SRST_SND 0x618
367 #define RK3562_GLB_RST_CON 0x61c
368 #define RK3562_GLB_RST_ST 0x620
369 #define RK3562_SDMMC0_CON0 0x624
370 #define RK3562_SDMMC0_CON1 0x628
371 #define RK3562_SDMMC1_CON0 0x62c
372 #define RK3562_SDMMC1_CON1 0x630
373
374 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
375 #define RK3568_MODE_CON0 0xc0
376 #define RK3568_MISC_CON0 0xc4
377 #define RK3568_MISC_CON1 0xc8
378 #define RK3568_MISC_CON2 0xcc
379 #define RK3568_GLB_CNT_TH 0xd0
380 #define RK3568_GLB_SRST_FST 0xd4
381 #define RK3568_GLB_SRST_SND 0xd8
382 #define RK3568_GLB_RST_CON 0xdc
383 #define RK3568_GLB_RST_ST 0xe0
384 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
385 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
386 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
387 #define RK3568_SDMMC0_CON0 0x580
388 #define RK3568_SDMMC0_CON1 0x584
389 #define RK3568_SDMMC1_CON0 0x588
390 #define RK3568_SDMMC1_CON1 0x58c
391 #define RK3568_SDMMC2_CON0 0x590
392 #define RK3568_SDMMC2_CON1 0x594
393 #define RK3568_EMMC_CON0 0x598
394 #define RK3568_EMMC_CON1 0x59c
395
396 #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
397 #define RK3568_PMU_MODE_CON0 0x80
398 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
399 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
400 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
401
402 #define RK3588_PHP_CRU_BASE 0x8000
403 #define RK3588_PMU_CRU_BASE 0x30000
404 #define RK3588_BIGCORE0_CRU_BASE 0x50000
405 #define RK3588_BIGCORE1_CRU_BASE 0x52000
406 #define RK3588_DSU_CRU_BASE 0x58000
407
408 #define RK3588_PLL_CON(x) RK2928_PLL_CON(x)
409 #define RK3588_MODE_CON0 0x280
410 #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280)
411 #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280)
412 #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280)
413 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
414 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
415 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
416 #define RK3588_GLB_CNT_TH 0xc00
417 #define RK3588_GLB_SRST_FST 0xc08
418 #define RK3588_GLB_SRST_SND 0xc0c
419 #define RK3588_GLB_RST_CON 0xc10
420 #define RK3588_GLB_RST_ST 0xc04
421 #define RK3588_SDIO_CON0 0xC24
422 #define RK3588_SDIO_CON1 0xC28
423 #define RK3588_SDMMC_CON0 0xC30
424 #define RK3588_SDMMC_CON1 0xC34
425
426 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
427 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
428
429 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
430 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
431 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
432 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
433
434 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
435 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
436 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
437 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
438 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
439 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
440 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
441 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
442 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
443 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
444 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
445 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
446
447 enum rockchip_pll_type {
448 pll_rk3036,
449 pll_rk3066,
450 pll_rk3328,
451 pll_rk3399,
452 pll_rk3588,
453 pll_rk3588_core,
454 };
455
456 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
457 _postdiv2, _dsmpd, _frac) \
458 { \
459 .rate = _rate##U, \
460 .fbdiv = _fbdiv, \
461 .postdiv1 = _postdiv1, \
462 .refdiv = _refdiv, \
463 .postdiv2 = _postdiv2, \
464 .dsmpd = _dsmpd, \
465 .frac = _frac, \
466 }
467
468 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
469 { \
470 .rate = _rate##U, \
471 .nr = _nr, \
472 .nf = _nf, \
473 .no = _no, \
474 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
475 }
476
477 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
478 { \
479 .rate = _rate##U, \
480 .nr = _nr, \
481 .nf = _nf, \
482 .no = _no, \
483 .nb = _nb, \
484 }
485
486 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
487 { \
488 .rate = _rate##U, \
489 .p = _p, \
490 .m = _m, \
491 .s = _s, \
492 .k = _k, \
493 }
494
495 /**
496 * struct rockchip_clk_provider - information about clock provider
497 * @reg_base: virtual address for the register base.
498 * @clk_data: holds clock related data like clk* and number of clocks.
499 * @cru_node: device-node of the clock-provider
500 * @grf: regmap of the general-register-files syscon
501 * @lock: maintains exclusion between callbacks for a given clock-provider.
502 */
503 struct rockchip_clk_provider {
504 void __iomem *reg_base;
505 struct clk_onecell_data clk_data;
506 struct device_node *cru_node;
507 struct regmap *grf;
508 struct regmap *pmugrf;
509 spinlock_t lock;
510 };
511
512 struct rockchip_pll_rate_table {
513 unsigned long rate;
514 union {
515 struct {
516 /* for RK3066 */
517 unsigned int nr;
518 unsigned int nf;
519 unsigned int no;
520 unsigned int nb;
521 };
522 struct {
523 /* for RK3036/RK3399 */
524 unsigned int fbdiv;
525 unsigned int postdiv1;
526 unsigned int refdiv;
527 unsigned int postdiv2;
528 unsigned int dsmpd;
529 unsigned int frac;
530 };
531 struct {
532 /* for RK3588 */
533 unsigned int m;
534 unsigned int p;
535 unsigned int s;
536 unsigned int k;
537 };
538 };
539 };
540
541 /**
542 * struct rockchip_pll_clock - information about pll clock
543 * @id: platform specific id of the clock.
544 * @name: name of this pll clock.
545 * @parent_names: name of the parent clock.
546 * @num_parents: number of parents
547 * @flags: optional flags for basic clock.
548 * @con_offset: offset of the register for configuring the PLL.
549 * @mode_offset: offset of the register for configuring the PLL-mode.
550 * @mode_shift: offset inside the mode-register for the mode of this pll.
551 * @lock_shift: offset inside the lock register for the lock status.
552 * @type: Type of PLL to be registered.
553 * @pll_flags: hardware-specific flags
554 * @rate_table: Table of usable pll rates
555 *
556 * Flags:
557 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
558 * rate_table parameters and ajust them if necessary.
559 */
560 struct rockchip_pll_clock {
561 unsigned int id;
562 const char *name;
563 const char *const *parent_names;
564 u8 num_parents;
565 unsigned long flags;
566 int con_offset;
567 int mode_offset;
568 int mode_shift;
569 int lock_shift;
570 enum rockchip_pll_type type;
571 u8 pll_flags;
572 struct rockchip_pll_rate_table *rate_table;
573 };
574
575 /*
576 * PLL flags
577 */
578 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
579 /* normal mode only. now only for pll_rk3036, pll_rk3328 type */
580 #define ROCKCHIP_PLL_FIXED_MODE BIT(1)
581 #define ROCKCHIP_PLL_ALLOW_POWER_DOWN BIT(2)
582
583 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
584 _lshift, _pflags, _rtable) \
585 { \
586 .id = _id, \
587 .type = _type, \
588 .name = _name, \
589 .parent_names = _pnames, \
590 .num_parents = ARRAY_SIZE(_pnames), \
591 .flags = CLK_GET_RATE_NOCACHE | _flags, \
592 .con_offset = _con, \
593 .mode_offset = _mode, \
594 .mode_shift = _mshift, \
595 .lock_shift = _lshift, \
596 .pll_flags = _pflags, \
597 .rate_table = _rtable, \
598 }
599
600 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
601 enum rockchip_pll_type pll_type,
602 const char *name, const char *const *parent_names,
603 u8 num_parents, int con_offset, int grf_lock_offset,
604 int lock_shift, int mode_offset, int mode_shift,
605 struct rockchip_pll_rate_table *rate_table,
606 unsigned long flags, u8 clk_pll_flags);
607
608 void rockchip_boost_init(struct clk_hw *hw);
609
610 void rockchip_boost_enable_recovery_sw_low(struct clk_hw *hw);
611
612 void rockchip_boost_disable_recovery_sw(struct clk_hw *hw);
613
614 void rockchip_boost_add_core_div(struct clk_hw *hw, unsigned long prate);
615
616 struct rockchip_cpuclk_clksel {
617 int reg;
618 u32 val;
619 };
620
621 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6
622 #define ROCKCHIP_CPUCLK_MAX_CORES 4
623 struct rockchip_cpuclk_rate_table {
624 unsigned long prate;
625 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
626 struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
627 struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
628 };
629
630 /**
631 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
632 * @core_reg[]: register offset of the cores setting register
633 * @div_core_shift[]: cores divider offset used to divide the pll value
634 * @div_core_mask[]: cores divider mask
635 * @num_cores: number of cpu cores
636 * @mux_core_reg: register offset of the cores select parent
637 * @mux_core_alt: mux value to select alternate parent
638 * @mux_core_main: mux value to select main parent of core
639 * @mux_core_shift: offset of the core multiplexer
640 * @mux_core_mask: core multiplexer mask
641 */
642 struct rockchip_cpuclk_reg_data {
643 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES];
644 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
645 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
646 int num_cores;
647 int mux_core_reg;
648 u8 mux_core_alt;
649 u8 mux_core_main;
650 u8 mux_core_shift;
651 u32 mux_core_mask;
652 const char *pll_name;
653 };
654
655 struct clk *rockchip_clk_register_cpuclk(const char *name,
656 u8 num_parents,
657 struct clk *parent, struct clk *alt_parent,
658 const struct rockchip_cpuclk_reg_data *reg_data,
659 const struct rockchip_cpuclk_rate_table *rates,
660 int nrates, void __iomem *reg_base, spinlock_t *lock);
661
662 struct clk *rockchip_clk_register_cpuclk_v2(const char *name,
663 const char *const *parent_names,
664 u8 num_parents, void __iomem *base,
665 int muxdiv_offset, u8 mux_shift,
666 u8 mux_width, u8 mux_flags,
667 int div_offset, u8 div_shift,
668 u8 div_width, u8 div_flags,
669 unsigned long flags, spinlock_t *lock,
670 const struct rockchip_cpuclk_rate_table *rates,
671 int nrates);
672
673 struct clk *rockchip_clk_register_mmc(const char *name,
674 const char *const *parent_names, u8 num_parents,
675 void __iomem *reg, int shift);
676
677 /*
678 * DDRCLK flags, including method of setting the rate
679 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
680 */
681 #define ROCKCHIP_DDRCLK_SIP BIT(0)
682 #define ROCKCHIP_DDRCLK_SIP_V2 0x03
683
684 #ifdef CONFIG_ROCKCHIP_DDRCLK
685 void rockchip_set_ddrclk_params(void __iomem *params);
686 void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void));
687
688 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
689 const char *const *parent_names,
690 u8 num_parents, int mux_offset,
691 int mux_shift, int mux_width,
692 int div_shift, int div_width,
693 int ddr_flags, void __iomem *reg_base);
694 #else
rockchip_set_ddrclk_params(void __iomem * params)695 static inline void rockchip_set_ddrclk_params(void __iomem *params) {}
rockchip_set_ddrclk_dmcfreq_wait_complete(int (* func)(void))696 static inline void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void)) {}
697 static inline
rockchip_clk_register_ddrclk(const char * name,int flags,const char * const * parent_names,u8 num_parents,int mux_offset,int mux_shift,int mux_width,int div_shift,int div_width,int ddr_flags,void __iomem * reg_base)698 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
699 const char *const *parent_names,
700 u8 num_parents, int mux_offset,
701 int mux_shift, int mux_width,
702 int div_shift, int div_width,
703 int ddr_flags, void __iomem *reg_base)
704 {
705 return NULL;
706 }
707 #endif
708
709 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
710
711 struct clk *rockchip_clk_register_inverter(const char *name,
712 const char *const *parent_names, u8 num_parents,
713 void __iomem *reg, int shift, int flags,
714 spinlock_t *lock);
715
716 struct clk *rockchip_clk_register_muxgrf(const char *name,
717 const char *const *parent_names, u8 num_parents,
718 int flags, struct regmap *grf, int reg,
719 int shift, int width, int mux_flags);
720
721 #define PNAME(x) static const char *const x[] __initconst
722
723 enum rockchip_clk_branch_type {
724 branch_composite,
725 branch_mux,
726 branch_muxgrf,
727 branch_muxpmugrf,
728 branch_divider,
729 branch_fraction_divider,
730 branch_gate,
731 branch_gate_no_set_rate,
732 branch_mmc,
733 branch_inverter,
734 branch_factor,
735 branch_ddrclk,
736 branch_half_divider,
737 };
738
739 struct rockchip_clk_branch {
740 unsigned int id;
741 enum rockchip_clk_branch_type branch_type;
742 const char *name;
743 const char *const *parent_names;
744 u8 num_parents;
745 unsigned long flags;
746 int muxdiv_offset;
747 u8 mux_shift;
748 u8 mux_width;
749 u8 mux_flags;
750 u32 *mux_table;
751 int div_offset;
752 u8 div_shift;
753 u8 div_width;
754 u8 div_flags;
755 struct clk_div_table *div_table;
756 int gate_offset;
757 u8 gate_shift;
758 u8 gate_flags;
759 struct rockchip_clk_branch *child;
760 };
761
762 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
763 df, go, gs, gf) \
764 { \
765 .id = _id, \
766 .branch_type = branch_composite, \
767 .name = cname, \
768 .parent_names = pnames, \
769 .num_parents = ARRAY_SIZE(pnames), \
770 .flags = f, \
771 .muxdiv_offset = mo, \
772 .mux_shift = ms, \
773 .mux_width = mw, \
774 .mux_flags = mf, \
775 .div_shift = ds, \
776 .div_width = dw, \
777 .div_flags = df, \
778 .gate_offset = go, \
779 .gate_shift = gs, \
780 .gate_flags = gf, \
781 }
782
783 #define COMPOSITE_MUXTBL(_id, cname, pnames, f, mo, ms, mw, mf, \
784 mt, ds, dw, df, go, gs, gf) \
785 { \
786 .id = _id, \
787 .branch_type = branch_composite, \
788 .name = cname, \
789 .parent_names = pnames, \
790 .num_parents = ARRAY_SIZE(pnames), \
791 .flags = f, \
792 .muxdiv_offset = mo, \
793 .mux_shift = ms, \
794 .mux_width = mw, \
795 .mux_flags = mf, \
796 .mux_table = mt, \
797 .div_shift = ds, \
798 .div_width = dw, \
799 .div_flags = df, \
800 .gate_offset = go, \
801 .gate_shift = gs, \
802 .gate_flags = gf, \
803 }
804
805 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
806 mf, do, ds, dw, df, go, gs, gf) \
807 { \
808 .id = _id, \
809 .branch_type = branch_composite, \
810 .name = cname, \
811 .parent_names = pnames, \
812 .num_parents = ARRAY_SIZE(pnames), \
813 .flags = f, \
814 .muxdiv_offset = mo, \
815 .mux_shift = ms, \
816 .mux_width = mw, \
817 .mux_flags = mf, \
818 .div_offset = do, \
819 .div_shift = ds, \
820 .div_width = dw, \
821 .div_flags = df, \
822 .gate_offset = go, \
823 .gate_shift = gs, \
824 .gate_flags = gf, \
825 }
826
827 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
828 go, gs, gf) \
829 { \
830 .id = _id, \
831 .branch_type = branch_composite, \
832 .name = cname, \
833 .parent_names = (const char *[]){ pname }, \
834 .num_parents = 1, \
835 .flags = f, \
836 .muxdiv_offset = mo, \
837 .div_shift = ds, \
838 .div_width = dw, \
839 .div_flags = df, \
840 .gate_offset = go, \
841 .gate_shift = gs, \
842 .gate_flags = gf, \
843 }
844
845 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
846 df, dt, go, gs, gf) \
847 { \
848 .id = _id, \
849 .branch_type = branch_composite, \
850 .name = cname, \
851 .parent_names = (const char *[]){ pname }, \
852 .num_parents = 1, \
853 .flags = f, \
854 .muxdiv_offset = mo, \
855 .div_shift = ds, \
856 .div_width = dw, \
857 .div_flags = df, \
858 .div_table = dt, \
859 .gate_offset = go, \
860 .gate_shift = gs, \
861 .gate_flags = gf, \
862 }
863
864 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
865 go, gs, gf) \
866 { \
867 .id = _id, \
868 .branch_type = branch_composite, \
869 .name = cname, \
870 .parent_names = pnames, \
871 .num_parents = ARRAY_SIZE(pnames), \
872 .flags = f, \
873 .muxdiv_offset = mo, \
874 .mux_shift = ms, \
875 .mux_width = mw, \
876 .mux_flags = mf, \
877 .gate_offset = go, \
878 .gate_shift = gs, \
879 .gate_flags = gf, \
880 }
881
882 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
883 ds, dw, df) \
884 { \
885 .id = _id, \
886 .branch_type = branch_composite, \
887 .name = cname, \
888 .parent_names = pnames, \
889 .num_parents = ARRAY_SIZE(pnames), \
890 .flags = f, \
891 .muxdiv_offset = mo, \
892 .mux_shift = ms, \
893 .mux_width = mw, \
894 .mux_flags = mf, \
895 .div_shift = ds, \
896 .div_width = dw, \
897 .div_flags = df, \
898 .gate_offset = -1, \
899 }
900
901 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
902 mw, mf, ds, dw, df, dt) \
903 { \
904 .id = _id, \
905 .branch_type = branch_composite, \
906 .name = cname, \
907 .parent_names = pnames, \
908 .num_parents = ARRAY_SIZE(pnames), \
909 .flags = f, \
910 .muxdiv_offset = mo, \
911 .mux_shift = ms, \
912 .mux_width = mw, \
913 .mux_flags = mf, \
914 .div_shift = ds, \
915 .div_width = dw, \
916 .div_flags = df, \
917 .div_table = dt, \
918 .gate_offset = -1, \
919 }
920
921 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
922 { \
923 .id = _id, \
924 .branch_type = branch_fraction_divider, \
925 .name = cname, \
926 .parent_names = (const char *[]){ pname }, \
927 .num_parents = 1, \
928 .flags = f, \
929 .muxdiv_offset = mo, \
930 .div_shift = 16, \
931 .div_width = 16, \
932 .div_flags = df, \
933 .gate_offset = go, \
934 .gate_shift = gs, \
935 .gate_flags = gf, \
936 }
937
938 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
939 { \
940 .id = _id, \
941 .branch_type = branch_fraction_divider, \
942 .name = cname, \
943 .parent_names = (const char *[]){ pname }, \
944 .num_parents = 1, \
945 .flags = f, \
946 .muxdiv_offset = mo, \
947 .div_shift = 16, \
948 .div_width = 16, \
949 .div_flags = df, \
950 .gate_offset = go, \
951 .gate_shift = gs, \
952 .gate_flags = gf, \
953 .child = ch, \
954 }
955
956 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
957 { \
958 .id = _id, \
959 .branch_type = branch_fraction_divider, \
960 .name = cname, \
961 .parent_names = (const char *[]){ pname }, \
962 .num_parents = 1, \
963 .flags = f, \
964 .muxdiv_offset = mo, \
965 .div_shift = 16, \
966 .div_width = 16, \
967 .div_flags = df, \
968 .gate_offset = -1, \
969 .child = ch, \
970 }
971
972 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
973 ds, dw, df) \
974 { \
975 .id = _id, \
976 .branch_type = branch_ddrclk, \
977 .name = cname, \
978 .parent_names = pnames, \
979 .num_parents = ARRAY_SIZE(pnames), \
980 .flags = f, \
981 .muxdiv_offset = mo, \
982 .mux_shift = ms, \
983 .mux_width = mw, \
984 .div_shift = ds, \
985 .div_width = dw, \
986 .div_flags = df, \
987 .gate_offset = -1, \
988 }
989
990 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
991 { \
992 .id = _id, \
993 .branch_type = branch_mux, \
994 .name = cname, \
995 .parent_names = pnames, \
996 .num_parents = ARRAY_SIZE(pnames), \
997 .flags = f, \
998 .muxdiv_offset = o, \
999 .mux_shift = s, \
1000 .mux_width = w, \
1001 .mux_flags = mf, \
1002 .gate_offset = -1, \
1003 }
1004
1005 #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
1006 { \
1007 .id = _id, \
1008 .branch_type = branch_mux, \
1009 .name = cname, \
1010 .parent_names = pnames, \
1011 .num_parents = ARRAY_SIZE(pnames), \
1012 .flags = f, \
1013 .muxdiv_offset = o, \
1014 .mux_shift = s, \
1015 .mux_width = w, \
1016 .mux_flags = mf, \
1017 .gate_offset = -1, \
1018 .mux_table = mt, \
1019 }
1020
1021 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
1022 { \
1023 .id = _id, \
1024 .branch_type = branch_muxgrf, \
1025 .name = cname, \
1026 .parent_names = pnames, \
1027 .num_parents = ARRAY_SIZE(pnames), \
1028 .flags = f, \
1029 .muxdiv_offset = o, \
1030 .mux_shift = s, \
1031 .mux_width = w, \
1032 .mux_flags = mf, \
1033 .gate_offset = -1, \
1034 }
1035
1036 #define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf) \
1037 { \
1038 .id = _id, \
1039 .branch_type = branch_muxpmugrf, \
1040 .name = cname, \
1041 .parent_names = pnames, \
1042 .num_parents = ARRAY_SIZE(pnames), \
1043 .flags = f, \
1044 .muxdiv_offset = o, \
1045 .mux_shift = s, \
1046 .mux_width = w, \
1047 .mux_flags = mf, \
1048 .gate_offset = -1, \
1049 }
1050
1051 #define DIV(_id, cname, pname, f, o, s, w, df) \
1052 { \
1053 .id = _id, \
1054 .branch_type = branch_divider, \
1055 .name = cname, \
1056 .parent_names = (const char *[]){ pname }, \
1057 .num_parents = 1, \
1058 .flags = f, \
1059 .muxdiv_offset = o, \
1060 .div_shift = s, \
1061 .div_width = w, \
1062 .div_flags = df, \
1063 .gate_offset = -1, \
1064 }
1065
1066 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
1067 { \
1068 .id = _id, \
1069 .branch_type = branch_divider, \
1070 .name = cname, \
1071 .parent_names = (const char *[]){ pname }, \
1072 .num_parents = 1, \
1073 .flags = f, \
1074 .muxdiv_offset = o, \
1075 .div_shift = s, \
1076 .div_width = w, \
1077 .div_flags = df, \
1078 .div_table = dt, \
1079 }
1080
1081 #define GATE(_id, cname, pname, f, o, b, gf) \
1082 { \
1083 .id = _id, \
1084 .branch_type = branch_gate, \
1085 .name = cname, \
1086 .parent_names = (const char *[]){ pname }, \
1087 .num_parents = 1, \
1088 .flags = f, \
1089 .gate_offset = o, \
1090 .gate_shift = b, \
1091 .gate_flags = gf, \
1092 }
1093
1094 #define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \
1095 { \
1096 .id = _id, \
1097 .branch_type = branch_gate_no_set_rate, \
1098 .name = cname, \
1099 .parent_names = (const char *[]){ pname }, \
1100 .num_parents = 1, \
1101 .flags = f, \
1102 .gate_offset = o, \
1103 .gate_shift = b, \
1104 .gate_flags = gf, \
1105 }
1106
1107 #define MMC(_id, cname, pname, offset, shift) \
1108 { \
1109 .id = _id, \
1110 .branch_type = branch_mmc, \
1111 .name = cname, \
1112 .parent_names = (const char *[]){ pname }, \
1113 .num_parents = 1, \
1114 .muxdiv_offset = offset, \
1115 .div_shift = shift, \
1116 }
1117
1118 #define INVERTER(_id, cname, pname, io, is, if) \
1119 { \
1120 .id = _id, \
1121 .branch_type = branch_inverter, \
1122 .name = cname, \
1123 .parent_names = (const char *[]){ pname }, \
1124 .num_parents = 1, \
1125 .muxdiv_offset = io, \
1126 .div_shift = is, \
1127 .div_flags = if, \
1128 }
1129
1130 #define FACTOR(_id, cname, pname, f, fm, fd) \
1131 { \
1132 .id = _id, \
1133 .branch_type = branch_factor, \
1134 .name = cname, \
1135 .parent_names = (const char *[]){ pname }, \
1136 .num_parents = 1, \
1137 .flags = f, \
1138 .div_shift = fm, \
1139 .div_width = fd, \
1140 }
1141
1142 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
1143 { \
1144 .id = _id, \
1145 .branch_type = branch_factor, \
1146 .name = cname, \
1147 .parent_names = (const char *[]){ pname }, \
1148 .num_parents = 1, \
1149 .flags = f, \
1150 .div_shift = fm, \
1151 .div_width = fd, \
1152 .gate_offset = go, \
1153 .gate_shift = gb, \
1154 .gate_flags = gf, \
1155 }
1156
1157 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
1158 df, go, gs, gf) \
1159 { \
1160 .id = _id, \
1161 .branch_type = branch_half_divider, \
1162 .name = cname, \
1163 .parent_names = pnames, \
1164 .num_parents = ARRAY_SIZE(pnames), \
1165 .flags = f, \
1166 .muxdiv_offset = mo, \
1167 .mux_shift = ms, \
1168 .mux_width = mw, \
1169 .mux_flags = mf, \
1170 .div_shift = ds, \
1171 .div_width = dw, \
1172 .div_flags = df, \
1173 .gate_offset = go, \
1174 .gate_shift = gs, \
1175 .gate_flags = gf, \
1176 }
1177
1178 #define COMPOSITE_HALFDIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, mf, do,\
1179 ds, dw, df, go, gs, gf) \
1180 { \
1181 .id = _id, \
1182 .branch_type = branch_half_divider, \
1183 .name = cname, \
1184 .parent_names = pnames, \
1185 .num_parents = ARRAY_SIZE(pnames), \
1186 .flags = f, \
1187 .muxdiv_offset = mo, \
1188 .mux_shift = ms, \
1189 .mux_width = mw, \
1190 .mux_flags = mf, \
1191 .div_offset = do, \
1192 .div_shift = ds, \
1193 .div_width = dw, \
1194 .div_flags = df, \
1195 .gate_offset = go, \
1196 .gate_shift = gs, \
1197 .gate_flags = gf, \
1198 }
1199
1200 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
1201 ds, dw, df) \
1202 { \
1203 .id = _id, \
1204 .branch_type = branch_half_divider, \
1205 .name = cname, \
1206 .parent_names = pnames, \
1207 .num_parents = ARRAY_SIZE(pnames), \
1208 .flags = f, \
1209 .muxdiv_offset = mo, \
1210 .mux_shift = ms, \
1211 .mux_width = mw, \
1212 .mux_flags = mf, \
1213 .div_shift = ds, \
1214 .div_width = dw, \
1215 .div_flags = df, \
1216 .gate_offset = -1, \
1217 }
1218
1219 #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \
1220 go, gs, gf) \
1221 { \
1222 .id = _id, \
1223 .branch_type = branch_half_divider, \
1224 .name = cname, \
1225 .parent_names = (const char *[]){ pname }, \
1226 .num_parents = 1, \
1227 .flags = f, \
1228 .muxdiv_offset = mo, \
1229 .div_shift = ds, \
1230 .div_width = dw, \
1231 .div_flags = df, \
1232 .gate_offset = go, \
1233 .gate_shift = gs, \
1234 .gate_flags = gf, \
1235 }
1236
1237 #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \
1238 { \
1239 .id = _id, \
1240 .branch_type = branch_half_divider, \
1241 .name = cname, \
1242 .parent_names = (const char *[]){ pname }, \
1243 .num_parents = 1, \
1244 .flags = f, \
1245 .muxdiv_offset = o, \
1246 .div_shift = s, \
1247 .div_width = w, \
1248 .div_flags = df, \
1249 .gate_offset = -1, \
1250 }
1251
1252 /* SGRF clocks are only accessible from secure mode, so not controllable */
1253 #define SGRF_GATE(_id, cname, pname) \
1254 FACTOR(_id, cname, pname, 0, 1, 1)
1255
1256 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
1257 void __iomem *base, unsigned long nr_clks);
1258 void rockchip_clk_of_add_provider(struct device_node *np,
1259 struct rockchip_clk_provider *ctx);
1260 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
1261 struct clk *clk, unsigned int id);
1262 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
1263 struct rockchip_clk_branch *list,
1264 unsigned int nr_clk);
1265 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
1266 struct rockchip_pll_clock *pll_list,
1267 unsigned int nr_pll, int grf_lock_offset);
1268 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
1269 unsigned int lookup_id,
1270 const char *name,
1271 u8 num_parents,
1272 struct clk *parent, struct clk *alt_parent,
1273 const struct rockchip_cpuclk_reg_data *reg_data,
1274 const struct rockchip_cpuclk_rate_table *rates,
1275 int nrates);
1276 void rockchip_clk_register_armclk_v2(struct rockchip_clk_provider *ctx,
1277 struct rockchip_clk_branch *list,
1278 const struct rockchip_cpuclk_rate_table *rates,
1279 int nrates);
1280 int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate);
1281 int rockchip_pll_clk_scale_to_rate(struct clk *clk, unsigned int scale);
1282 int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel);
1283 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
1284 unsigned int reg, void (*cb)(void));
1285
1286 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
1287
1288 struct clk *rockchip_clk_register_halfdiv(const char *name,
1289 const char *const *parent_names,
1290 u8 num_parents, void __iomem *base,
1291 int muxdiv_offset, u8 mux_shift,
1292 u8 mux_width, u8 mux_flags,
1293 int div_offset, u8 div_shift,
1294 u8 div_width, u8 div_flags,
1295 int gate_offset, u8 gate_shift,
1296 u8 gate_flags, unsigned long flags,
1297 spinlock_t *lock);
1298
1299 #ifdef CONFIG_RESET_CONTROLLER
1300 void rockchip_register_softrst(struct device_node *np,
1301 unsigned int num_regs,
1302 void __iomem *base, u8 flags);
1303 #else
rockchip_register_softrst(struct device_node * np,unsigned int num_regs,void __iomem * base,u8 flags)1304 static inline void rockchip_register_softrst(struct device_node *np,
1305 unsigned int num_regs,
1306 void __iomem *base, u8 flags)
1307 {
1308 }
1309 #endif
1310 extern void (*rk_dump_cru)(void);
1311
1312 #if IS_MODULE(CONFIG_COMMON_CLK_ROCKCHIP)
1313 int rockchip_clk_protect(struct rockchip_clk_provider *ctx,
1314 unsigned int *clocks, unsigned int nclocks);
1315 void rockchip_clk_unprotect(void);
1316 #else
rockchip_clk_protect(struct rockchip_clk_provider * ctx,unsigned int * clocks,unsigned int nclocks)1317 static inline int rockchip_clk_protect(struct rockchip_clk_provider *ctx,
1318 unsigned int *clocks,
1319 unsigned int nclocks)
1320 {
1321 return -EOPNOTSUPP;
1322 }
1323
rockchip_clk_unprotect(void)1324 static inline void rockchip_clk_unprotect(void)
1325 {
1326 }
1327 #endif
1328 #endif
1329