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Searched refs:ccu (Results 1 – 25 of 55) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-kona.c130 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) in __ccu_read() argument
132 return readl(ccu->base + reg_offset); in __ccu_read()
137 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
139 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
142 static inline unsigned long ccu_lock(struct ccu_data *ccu) in ccu_lock() argument
146 spin_lock_irqsave(&ccu->lock, flags); in ccu_lock()
150 static inline void ccu_unlock(struct ccu_data *ccu, unsigned long flags) in ccu_unlock() argument
152 spin_unlock_irqrestore(&ccu->lock, flags); in ccu_unlock()
159 static inline void __ccu_write_enable(struct ccu_data *ccu) in __ccu_write_enable() argument
161 if (ccu->write_enabled) { in __ccu_write_enable()
[all …]
H A Dclk-kona-setup.c26 static bool ccu_data_offsets_valid(struct ccu_data *ccu) in ccu_data_offsets_valid() argument
28 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
31 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
37 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
43 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
93 range = bcm_clk->ccu->range; in peri_clk_data_offsets_valid()
747 static void ccu_clks_teardown(struct ccu_data *ccu) in ccu_clks_teardown() argument
751 for (i = 0; i < ccu->clk_num; i++) in ccu_clks_teardown()
752 kona_clk_teardown(&ccu->kona_clks[i].hw); in ccu_clks_teardown()
755 static void kona_ccu_teardown(struct ccu_data *ccu) in kona_ccu_teardown() argument
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsun6i-a31.dtsi48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
106 clocks = <&ccu CLK_CPU>;
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H A Dsunxi-h3-h5.dtsi44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
75 <&ccu CLK_TVE>;
118 clocks = <&ccu CLK_BUS_DE>,
119 <&ccu CLK_DE>;
122 resets = <&ccu RST_BUS_DE>;
154 clocks = <&ccu CLK_BUS_DMA>;
[all …]
H A Dsun4i-a10.dtsi46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
[all …]
H A Dsun8i-r40.dtsi46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
140 clocks = <&ccu CLK_BUS_DE>,
141 <&ccu CLK_DE>;
144 resets = <&ccu RST_BUS_DE>;
229 clocks = <&ccu CLK_BUS_DMA>;
232 resets = <&ccu RST_BUS_DMA>;
241 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
243 resets = <&ccu RST_BUS_SPI0>;
254 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
[all …]
H A Dsun8i-v3s.dtsi44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
63 <&ccu CLK_TCON0>;
76 clocks = <&ccu CLK_CPU>;
125 clocks = <&ccu CLK_BUS_DE>,
126 <&ccu CLK_DE>;
129 resets = <&ccu RST_BUS_DE>;
170 clocks = <&ccu CLK_BUS_TCON0>,
171 <&ccu CLK_TCON0>;
176 resets = <&ccu RST_BUS_TCON0>;
[all …]
H A Dsun7i-a20.dtsi48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
70 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
71 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
72 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
73 <&ccu CLK_HDMI>;
81 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
82 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
83 <&ccu CLK_DRAM_DE_BE0>;
91 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
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H A Dsun8i-a83t.dtsi47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
67 clocks = <&ccu CLK_C0CPUX>;
78 clocks = <&ccu CLK_C0CPUX>;
89 clocks = <&ccu CLK_C0CPUX>;
100 clocks = <&ccu CLK_C0CPUX>;
111 clocks = <&ccu CLK_C1CPUX>;
122 clocks = <&ccu CLK_C1CPUX>;
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H A Dsun8i-a23-a33.dtsi47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
159 clocks = <&ccu CLK_BUS_DMA>;
160 resets = <&ccu RST_BUS_DMA>;
168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
170 resets = <&ccu RST_BUS_NAND>;
186 clocks = <&ccu CLK_BUS_LCD>,
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H A Dsun5i.dtsi45 #include <dt-bindings/clock/sun5i-ccu.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
62 clocks = <&ccu CLK_CPU>;
75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
85 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
86 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
188 clocks = <&ccu CLK_MBUS>;
199 clocks = <&ccu CLK_AHB_DMA>;
[all …]
H A Dsun8i-h3.dtsi78 clocks = <&ccu CLK_CPUX>;
88 clocks = <&ccu CLK_CPUX>;
98 clocks = <&ccu CLK_CPUX>;
108 clocks = <&ccu CLK_CPUX>;
156 clocks = <&ccu CLK_BUS_DEINTERLACE>,
157 <&ccu CLK_DEINTERLACE>,
158 <&ccu CLK_DRAM_DEINTERLACE>;
160 resets = <&ccu RST_BUS_DEINTERLACE>;
191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
192 <&ccu CLK_DRAM_VE>;
[all …]
H A Dsun8i-a33.dtsi128 clocks = <&ccu CLK_CPUX>;
135 clocks = <&ccu CLK_CPUX>;
145 clocks = <&ccu CLK_CPUX>;
155 clocks = <&ccu CLK_CPUX>;
209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
210 <&ccu CLK_DRAM_VE>;
212 resets = <&ccu RST_BUS_VE>;
221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
223 resets = <&ccu RST_BUS_SS>;
232 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
[all …]
H A Dsun9i-a80.dtsi47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
226 <&ccu CLK_PLL_PERIPH0>,
227 <&ccu CLK_PLL_AUDIO>;
326 clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
328 resets = <&ccu RST_BUS_GMAC>;
449 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
464 resets = <&ccu RST_BUS_SS>;
465 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
472 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
[all …]
H A Dsun5i-a10s.dtsi63 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
64 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
65 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
81 <&ccu CLK_PLL_VIDEO0_2X>,
82 <&ccu CLK_PLL_VIDEO1_2X>;
111 clocks = <&ccu CLK_HOSC>;
118 &ccu {
119 compatible = "allwinner,sun5i-a10s-ccu";
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A DMakefile24 obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
25 obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
26 obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
27 obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
28 obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
29 obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
30 obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
31 obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
32 obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
33 obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
[all …]
H A Dccu_reset.c16 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_assert() local
17 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_assert()
21 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_assert()
23 reg = readl(ccu->base + map->reg); in ccu_reset_assert()
24 writel(reg & ~map->bit, ccu->base + map->reg); in ccu_reset_assert()
26 spin_unlock_irqrestore(ccu->lock, flags); in ccu_reset_assert()
34 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_deassert() local
35 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_deassert()
39 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_deassert()
41 reg = readl(ccu->base + map->reg); in ccu_reset_deassert()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6.dtsi5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
28 clocks = <&ccu CLK_CPUX>;
38 clocks = <&ccu CLK_CPUX>;
48 clocks = <&ccu CLK_CPUX>;
58 clocks = <&ccu CLK_CPUX>;
122 clocks = <&ccu CLK_DE>,
123 <&ccu CLK_BUS_DE>;
[all …]
H A Dsun50i-a64.dtsi6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
29 clocks = <&ccu CLK_TCON0>,
39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
54 clocks = <&ccu CLK_CPUX>;
65 clocks = <&ccu CLK_CPUX>;
76 clocks = <&ccu CLK_CPUX>;
87 clocks = <&ccu CLK_CPUX>;
[all …]
H A Dsun50i-h5.dtsi18 clocks = <&ccu CLK_CPUX>;
28 clocks = <&ccu CLK_CPUX>;
38 clocks = <&ccu CLK_CPUX>;
48 clocks = <&ccu CLK_CPUX>;
107 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
108 <&ccu CLK_DRAM_VE>;
110 resets = <&ccu RST_BUS_VE>;
119 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
121 resets = <&ccu RST_BUS_CE>;
155 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
[all …]
H A Dsun50i-a100.dtsi7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
95 ccu: clock@3001000 { label
96 compatible = "allwinner,sun50i-a100-ccu";
136 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
155 clocks = <&ccu CLK_BUS_UART0>;
156 resets = <&ccu RST_BUS_UART0>;
166 clocks = <&ccu CLK_BUS_UART1>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun8i-h3.dtsi45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
156 clocks = <&ccu CLK_BUS_DMA>;
157 resets = <&ccu RST_BUS_DMA>;
165 clocks = <&ccu CLK_BUS_MMC0>,
166 <&ccu CLK_MMC0>,
167 <&ccu CLK_MMC0_OUTPUT>,
168 <&ccu CLK_MMC0_SAMPLE>;
173 resets = <&ccu RST_BUS_MMC0>;
185 clocks = <&ccu CLK_BUS_MMC1>,
[all …]
H A Dsun50i-a64.dtsi45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
47 #include <dt-bindings/reset/sun50i-a64-ccu.h>
135 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
137 resets = <&ccu RST_BUS_MMC0>;
149 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
151 resets = <&ccu RST_BUS_MMC1>;
163 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
165 resets = <&ccu RST_BUS_MMC2>;
177 clocks = <&ccu CLK_BUS_OTG>;
178 resets = <&ccu RST_BUS_OTG>;
[all …]
H A Dsun8i-v3s.dtsi43 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
44 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
61 clocks = <&ccu CLK_CPU>;
102 clocks = <&ccu CLK_BUS_MMC0>,
103 <&ccu CLK_MMC0>,
104 <&ccu CLK_MMC0_OUTPUT>,
105 <&ccu CLK_MMC0_SAMPLE>;
110 resets = <&ccu RST_BUS_MMC0>;
121 clocks = <&ccu CLK_BUS_MMC1>,
122 <&ccu CLK_MMC1>,
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/mpp/
H A Dmpp_vepu2.c129 struct vepu_ccu *ccu; member
318 struct vepu_ccu *ccu = enc->ccu; in vepu_prepare() local
324 spin_lock_irqsave(&ccu->lock, flags); in vepu_prepare()
326 core_idle = ccu->core_idle; in vepu_prepare()
328 for (i = 0; i < ccu->core_num; i++) { in vepu_prepare()
329 struct mpp_dev *mpp = ccu->cores[i]; in vepu_prepare()
335 core_id = find_first_bit(&core_idle, ccu->core_num); in vepu_prepare()
336 if (core_id >= ARRAY_SIZE(ccu->cores)) { in vepu_prepare()
338 mpp_dbg_core("core %d all busy %lx\n", core_id, ccu->core_idle); in vepu_prepare()
343 clear_bit(core_id, &ccu->core_idle); in vepu_prepare()
[all …]

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