1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Maxime Ripard
4*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/reset-controller.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ccu_reset.h"
12*4882a593Smuzhiyun
ccu_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)13*4882a593Smuzhiyun static int ccu_reset_assert(struct reset_controller_dev *rcdev,
14*4882a593Smuzhiyun unsigned long id)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
17*4882a593Smuzhiyun const struct ccu_reset_map *map = &ccu->reset_map[id];
18*4882a593Smuzhiyun unsigned long flags;
19*4882a593Smuzhiyun u32 reg;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun spin_lock_irqsave(ccu->lock, flags);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun reg = readl(ccu->base + map->reg);
24*4882a593Smuzhiyun writel(reg & ~map->bit, ccu->base + map->reg);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun spin_unlock_irqrestore(ccu->lock, flags);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
ccu_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)31*4882a593Smuzhiyun static int ccu_reset_deassert(struct reset_controller_dev *rcdev,
32*4882a593Smuzhiyun unsigned long id)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
35*4882a593Smuzhiyun const struct ccu_reset_map *map = &ccu->reset_map[id];
36*4882a593Smuzhiyun unsigned long flags;
37*4882a593Smuzhiyun u32 reg;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun spin_lock_irqsave(ccu->lock, flags);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun reg = readl(ccu->base + map->reg);
42*4882a593Smuzhiyun writel(reg | map->bit, ccu->base + map->reg);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun spin_unlock_irqrestore(ccu->lock, flags);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
ccu_reset_reset(struct reset_controller_dev * rcdev,unsigned long id)49*4882a593Smuzhiyun static int ccu_reset_reset(struct reset_controller_dev *rcdev,
50*4882a593Smuzhiyun unsigned long id)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun ccu_reset_assert(rcdev, id);
53*4882a593Smuzhiyun udelay(10);
54*4882a593Smuzhiyun ccu_reset_deassert(rcdev, id);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
ccu_reset_status(struct reset_controller_dev * rcdev,unsigned long id)59*4882a593Smuzhiyun static int ccu_reset_status(struct reset_controller_dev *rcdev,
60*4882a593Smuzhiyun unsigned long id)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
63*4882a593Smuzhiyun const struct ccu_reset_map *map = &ccu->reset_map[id];
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * The reset control API expects 0 if reset is not asserted,
67*4882a593Smuzhiyun * which is the opposite of what our hardware uses.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun return !(map->bit & readl(ccu->base + map->reg));
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun const struct reset_control_ops ccu_reset_ops = {
73*4882a593Smuzhiyun .assert = ccu_reset_assert,
74*4882a593Smuzhiyun .deassert = ccu_reset_deassert,
75*4882a593Smuzhiyun .reset = ccu_reset_reset,
76*4882a593Smuzhiyun .status = ccu_reset_status,
77*4882a593Smuzhiyun };
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