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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/lib/gcc/aarch64-none-linux-gnu/10.3.1/plugin/include/
H A Dtree-data-ref.h487 #define DDR_A(DDR) (DDR)->a argument
488 #define DDR_B(DDR) (DDR)->b argument
489 #define DDR_AFFINE_P(DDR) (DDR)->affine_p argument
490 #define DDR_ARE_DEPENDENT(DDR) (DDR)->are_dependent argument
491 #define DDR_OBJECT_A(DDR) (DDR)->object_a argument
492 #define DDR_OBJECT_B(DDR) (DDR)->object_b argument
493 #define DDR_SUBSCRIPTS(DDR) (DDR)->subscripts argument
494 #define DDR_SUBSCRIPT(DDR, I) DDR_SUBSCRIPTS (DDR)[I] argument
495 #define DDR_NUM_SUBSCRIPTS(DDR) DDR_SUBSCRIPTS (DDR).length () argument
497 #define DDR_LOOP_NEST(DDR) (DDR)->loop_nest argument
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/lib/gcc/arm-none-linux-gnueabihf/10.3.1/plugin/include/
H A Dtree-data-ref.h487 #define DDR_A(DDR) (DDR)->a argument
488 #define DDR_B(DDR) (DDR)->b argument
489 #define DDR_AFFINE_P(DDR) (DDR)->affine_p argument
490 #define DDR_ARE_DEPENDENT(DDR) (DDR)->are_dependent argument
491 #define DDR_OBJECT_A(DDR) (DDR)->object_a argument
492 #define DDR_OBJECT_B(DDR) (DDR)->object_b argument
493 #define DDR_SUBSCRIPTS(DDR) (DDR)->subscripts argument
494 #define DDR_SUBSCRIPT(DDR, I) DDR_SUBSCRIPTS (DDR)[I] argument
495 #define DDR_NUM_SUBSCRIPTS(DDR) DDR_SUBSCRIPTS (DDR).length () argument
497 #define DDR_LOOP_NEST(DDR) (DDR)->loop_nest argument
[all …]
/OK3568_Linux_fs/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg24 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
27 # bit24: 1= enable exit self refresh mode on DDR access
32 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
43 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
61 DATA 0xFFD01410 0x000000cc # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg27 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
30 # bit24: 1= enable exit self refresh mode on DDR access
35 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
46 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
57 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
64 DATA 0xFFD01410 0x0000000d # DDR Address Control
79 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
83 DATA 0xFFD01418 0x00000000 # DDR Operation
84 # bit3-0: 0x0, DDR cmd
87 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg28 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
31 # bit24: 1= enable exit self refresh mode on DDR access
36 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
47 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
58 DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
65 DATA 0xFFD01410 0x0000000d # DDR Address Control
80 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
84 DATA 0xFFD01418 0x00000000 # DDR Operation
85 # bit3-0: 0x0, DDR cmd
88 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg25 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
28 # bit24: 1= enable exit self refresh mode on DDR access
33 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
44 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
55 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
62 DATA 0xFFD01410 0x000000cc # DDR Address Control
77 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
81 DATA 0xFFD01418 0x00000000 # DDR Operation
82 # bit3-0: 0x0, DDR cmd
85 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg30 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
33 # bit24: 1= enable exit self refresh mode on DDR access
38 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
49 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
60 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
67 DATA 0xFFD01410 0x0000000d # DDR Address Control
82 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
86 DATA 0xFFD01418 0x00000000 # DDR Operation
87 # bit3-0: 0x0, DDR cmd
90 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg24 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
27 # bit24: 1= enable exit self refresh mode on DDR access
32 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
43 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
61 DATA 0xFFD01410 0x000000cc # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg27 DATA 0xFFD01400 0x43000618 # DDR Configuration register
30 # bit24: 1= enable exit self refresh mode on DDR access
35 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
46 DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
56 DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
64 DATA 0xFFD01410 0x0000000d # DDR Address Control
79 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
83 DATA 0xFFD01418 0x00000000 # DDR Operation
84 # bit3-0: 0x0, DDR cmd
87 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg24 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
27 # bit24: 1= enable exit self refresh mode on DDR access
32 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
43 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
61 DATA 0xFFD01410 0x000000cc # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg24 DATA 0xffd01400 0x43000c30 # DDR Configuration register
27 # bit24: 0x1, enable exit self refresh mode on DDR access
32 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
43 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
61 DATA 0xffd01410 0x000000cc # DDR Address Control
76 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
80 DATA 0xffd01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xffd0141c 0x00000c52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg25 DATA 0xFFD01400 0x43000C30 # DDR Configuration register
28 # bit24: 1= enable exit self refresh mode on DDR access
33 DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
44 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
61 DATA 0xFFD01410 0x0000CCCC # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000662 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg25 DATA 0xffd01400 0x43000c30 # DDR Configuration register
28 # bit24: 0x1, enable exit self refresh mode on DDR access
33 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
44 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
55 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
62 DATA 0xffd01410 0x0000000c # DDR Address Control
77 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
81 DATA 0xffd01418 0x00000000 # DDR Operation
82 # bit3-0: 0x0, DDR cmd
85 DATA 0xffd0141c 0x00000c52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage-ns2l.cfg25 DATA 0xFFD01400 0x43000618 # DDR Configuration register
28 # bit24: 1= enable exit self refresh mode on DDR access
33 DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
44 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
61 DATA 0xFFD01410 0x0000DDDD # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
H A Dkwbimage-is2.cfg25 DATA 0xFFD01400 0x43000618 # DDR Configuration register
28 # bit24: 1= enable exit self refresh mode on DDR access
33 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
44 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
61 DATA 0xFFD01410 0x00000008 # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
H A Dkwbimage.cfg25 DATA 0xFFD01400 0x43000618 # DDR Configuration register
28 # bit24: 1= enable exit self refresh mode on DDR access
33 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
44 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
61 DATA 0xFFD01410 0x0000000C # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg28 DATA 0xffd01400 0x43000c30 # DDR Configuration register
31 # bit24: 1= enable exit self refresh mode on DDR access
36 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
47 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
58 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
65 DATA 0xffd01410 0x000000cc # DDR Address Control
80 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
84 DATA 0xffd01418 0x00000000 # DDR Operation
85 # bit3-0: 0x0, DDR cmd
88 DATA 0xffd0141c 0x00000c52 # DDR Mode
[all …]
/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg47 # bit24: 1= enable exit self refresh mode on DDR access
52 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
64 DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
75 DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
82 DATA 0xFFD01410 0x0000000D # DDR Address Control
97 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
101 DATA 0xFFD01418 0x00000000 # DDR Operation
102 # bit3-0: 0x0, DDR cmd
105 DATA 0xFFD0141C 0x00000652 # DDR Mode
106 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
[all …]
H A Dkwbimage-memphis.cfg50 # bit24: 1= enable exit self refresh mode on DDR access
55 DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
67 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
78 DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
85 DATA 0xFFD01410 0x00000001 # DDR Address Control
100 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
104 DATA 0xFFD01418 0x00000000 # DDR Operation
105 # bit3-0: 0x0, DDR cmd
108 DATA 0xFFD0141C 0x00000652 # DDR Mode
109 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
[all …]
H A Dkwbimage_128M16_1.cfg97 # bit 24: 1, enable exit self refresh mode on DDR access
102 DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
118 DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
129 DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
136 DATA 0xFFD01410 0x00000001 # DDR Address Control
151 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
155 DATA 0xFFD01418 0x00000000 # DDR Operation
156 # bit 3-0: 0, DDR cmd
159 DATA 0xFFD0141C 0x00000652 # DDR Mode
170 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.ramboot-ppc85xx4 RAMBOOT literally means boot from DDR. But since DDR is volatile memory some
5 pre-mechanism is required to load the DDR with the bootloader binary.
9 which can initialize the DDR and get the complete bootloader copied to DDR.
11 In addition to the above there could be some more methods to initialize the DDR
15 1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
16 execute the bootloader from DDR.
22 2. Load the RAM based bootloader onto DDR using already existing bootloader on
23 the board.And then execute the bootloader from DDR.
29 In this case you can get your test bootloader binary into DDR via tftp
51 Preconfigure DDR/L2SRAM through JTAG interface.
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
45 address mode. This mode can use 128MB DDR-SDRAM.
48 extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
49 "pmb" command, this mode can use 512MB DDR-SDRAM.
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
64 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
65 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
[all …]
/OK3568_Linux_fs/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg28 # DDR Configuration register
32 # bit24: 1, enable exit self refresh mode on DDR access
37 # DDR Controller Control Low
55 # DDR Timing (Low)
67 # DDR Timing (High)
75 # DDR Address Control
91 # DDR Open Pages Control
96 # DDR Operation
101 # DDR Mode
112 # DDR Extended Mode
[all …]
H A Dkwbimage-lsxhl.cfg28 # DDR Configuration register
32 # bit24: 1, enable exit self refresh mode on DDR access
37 # DDR Controller Control Low
55 # DDR Timing (Low)
67 # DDR Timing (High)
75 # DDR Address Control
91 # DDR Open Pages Control
96 # DDR Operation
101 # DDR Mode
112 # DDR Extended Mode
[all …]
/OK3568_Linux_fs/rkbin/doc/release/
H A DRK3568_CN.md13 | 1 | 重要 | 修正DDR active_ranks配置错误引起的休眠唤醒死机问题 | 休眠唤醒异常 | - |
38 2. 增加DDR ECC poison功能支持。
110 | 1 | 普通 | 修改DDR ECC错误注入功能的smc_handler ID | DDR ECC错误注入功能异常失效 | - |
146 1. 增加DDR ECC错误注入。
230 | 1 | 重要 | 解决部分主控在DDR 324MHz下的不稳定问题 | 在DDR 324MHz下，系统不稳定，出现死机重启 | - |
244 | 1 | 重要 | 解决部分主控在DDR 324MHz下的不稳定问题 | 在DDR 324MHz下，系统不稳定，出现死机重启 | - |

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