Lines Matching refs:DDR
24 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
27 # bit24: 1= enable exit self refresh mode on DDR access
32 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
43 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
61 DATA 0xFFD01410 0x000000cc # DDR Address Control
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xFFD0141C 0x00000C52 # DDR Mode
94 DATA 0xFFD01420 0x00000042 # DDR Extended Mode
95 # bit0: 0, DDR DLL enabled
96 # bit1: 1, DDR drive strength reduced
97 # bit2: 0, DDR ODT control lsd (disabled)
99 # bit6: 1, DDR ODT control msb, (disabled)
103 # bit12: 0, DDR output buffer enabled
106 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
135 DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
140 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
147 # bit15: 1, DDR IO ODT Unit: Use ODT block
148 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
149 #bit0=1, enable DDR init upon this register write