1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# (C) Copyright 2010 3*4882a593Smuzhiyun# Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun# 7*4882a593Smuzhiyun# Refer doc/README.kwbimage for more details about how-to configure 8*4882a593Smuzhiyun# and create kirkwood boot image 9*4882a593Smuzhiyun# 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun# Boot Media configurations 12*4882a593SmuzhiyunBOOT_FROM spi # Boot from SPI flash 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunDATA 0xFFD10000 0x01112222 # MPP Control 0 Register 15*4882a593Smuzhiyun# bit 3-0: MPPSel0 2, NF_IO[2] 16*4882a593Smuzhiyun# bit 7-4: MPPSel1 2, NF_IO[3] 17*4882a593Smuzhiyun# bit 12-8: MPPSel2 2, NF_IO[4] 18*4882a593Smuzhiyun# bit 15-12: MPPSel3 2, NF_IO[5] 19*4882a593Smuzhiyun# bit 19-16: MPPSel4 1, NF_IO[6] 20*4882a593Smuzhiyun# bit 23-20: MPPSel5 1, NF_IO[7] 21*4882a593Smuzhiyun# bit 27-24: MPPSel6 1, SYSRST_O 22*4882a593Smuzhiyun# bit 31-28: MPPSel7 0, GPO[7] 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunDATA 0xFFD10004 0x03303300 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunDATA 0xFFD10008 0x00001100 # MPP Control 2 Register 27*4882a593Smuzhiyun# bit 3-0: MPPSel16 0, GPIO[16] 28*4882a593Smuzhiyun# bit 7-4: MPPSel17 0, GPIO[17] 29*4882a593Smuzhiyun# bit 12-8: MPPSel18 1, NF_IO[0] 30*4882a593Smuzhiyun# bit 15-12: MPPSel19 1, NF_IO[1] 31*4882a593Smuzhiyun# bit 19-16: MPPSel20 0, GPIO[20] 32*4882a593Smuzhiyun# bit 23-20: MPPSel21 0, GPIO[21] 33*4882a593Smuzhiyun# bit 27-24: MPPSel22 0, GPIO[22] 34*4882a593Smuzhiyun# bit 31-28: MPPSel23 0, GPIO[23] 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunDATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 37*4882a593SmuzhiyunDATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 38*4882a593SmuzhiyunDATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! 41*4882a593Smuzhiyun# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun#Dram initalization 44*4882a593SmuzhiyunDATA 0xFFD01400 0x43000400 # SDRAM Configuration Register 45*4882a593Smuzhiyun# bit13-0: 0x400 (DDR2 clks refresh rate) 46*4882a593Smuzhiyun# bit23-14: zero 47*4882a593Smuzhiyun# bit24: 1= enable exit self refresh mode on DDR access 48*4882a593Smuzhiyun# bit25: 1 required 49*4882a593Smuzhiyun# bit29-26: zero 50*4882a593Smuzhiyun# bit31-30: 01 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunDATA 0xFFD01404 0x39543000 # DDR Controller Control Low 53*4882a593Smuzhiyun# bit 3-0: 0 reserved 54*4882a593Smuzhiyun# bit 4: 0=addr/cmd in smame cycle 55*4882a593Smuzhiyun# bit 5: 0=clk is driven during self refresh, we don't care for APX 56*4882a593Smuzhiyun# bit 6: 0=use recommended falling edge of clk for addr/cmd 57*4882a593Smuzhiyun# bit14: 0=input buffer always powered up 58*4882a593Smuzhiyun# bit18: 1=cpu lock transaction enabled 59*4882a593Smuzhiyun# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 60*4882a593Smuzhiyun# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 61*4882a593Smuzhiyun# bit30-28: 3 required 62*4882a593Smuzhiyun# bit31: 0=no additional STARTBURST delay 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunDATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) 65*4882a593Smuzhiyun# bit3-0: TRAS lsbs 66*4882a593Smuzhiyun# bit7-4: TRCD 67*4882a593Smuzhiyun# bit11- 8: TRP 68*4882a593Smuzhiyun# bit15-12: TWR 69*4882a593Smuzhiyun# bit19-16: TWTR 70*4882a593Smuzhiyun# bit20: TRAS msb 71*4882a593Smuzhiyun# bit23-21: 0x0 72*4882a593Smuzhiyun# bit27-24: TRRD 73*4882a593Smuzhiyun# bit31-28: TRTP 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunDATA 0xFFD0140C 0x00000033 # DDR Timing (High) 76*4882a593Smuzhiyun# bit6-0: TRFC 77*4882a593Smuzhiyun# bit8-7: TR2R 78*4882a593Smuzhiyun# bit10-9: TR2W 79*4882a593Smuzhiyun# bit12-11: TW2W 80*4882a593Smuzhiyun# bit31-13: zero required 81*4882a593Smuzhiyun 82*4882a593SmuzhiyunDATA 0xFFD01410 0x0000000D # DDR Address Control 83*4882a593Smuzhiyun# bit1-0: 01, Cs0width=x16 84*4882a593Smuzhiyun# bit3-2: 11, Cs0size=1Gb 85*4882a593Smuzhiyun# bit5-4: 00, Cs2width=nonexistent 86*4882a593Smuzhiyun# bit7-6: 00, Cs1size =nonexistent 87*4882a593Smuzhiyun# bit9-8: 00, Cs2width=nonexistent 88*4882a593Smuzhiyun# bit11-10: 00, Cs2size =nonexistent 89*4882a593Smuzhiyun# bit13-12: 00, Cs3width=nonexistent 90*4882a593Smuzhiyun# bit15-14: 00, Cs3size =nonexistent 91*4882a593Smuzhiyun# bit16: 0, Cs0AddrSel 92*4882a593Smuzhiyun# bit17: 0, Cs1AddrSel 93*4882a593Smuzhiyun# bit18: 0, Cs2AddrSel 94*4882a593Smuzhiyun# bit19: 0, Cs3AddrSel 95*4882a593Smuzhiyun# bit31-20: 0 required 96*4882a593Smuzhiyun 97*4882a593SmuzhiyunDATA 0xFFD01414 0x00000000 # DDR Open Pages Control 98*4882a593Smuzhiyun# bit0: 0, OpenPage enabled 99*4882a593Smuzhiyun# bit31-1: 0 required 100*4882a593Smuzhiyun 101*4882a593SmuzhiyunDATA 0xFFD01418 0x00000000 # DDR Operation 102*4882a593Smuzhiyun# bit3-0: 0x0, DDR cmd 103*4882a593Smuzhiyun# bit31-4: 0 required 104*4882a593Smuzhiyun 105*4882a593SmuzhiyunDATA 0xFFD0141C 0x00000652 # DDR Mode 106*4882a593SmuzhiyunDATA 0xFFD01420 0x00000044 # DDR Extended Mode 107*4882a593Smuzhiyun# bit0: 0, DDR DLL enabled 108*4882a593Smuzhiyun# bit1: 0, DDR drive strenght normal 109*4882a593Smuzhiyun# bit2: 1, DDR ODT control lsd disabled 110*4882a593Smuzhiyun# bit5-3: 000, required 111*4882a593Smuzhiyun# bit6: 1, DDR ODT control msb, enabled 112*4882a593Smuzhiyun# bit9-7: 000, required 113*4882a593Smuzhiyun# bit10: 0, differential DQS enabled 114*4882a593Smuzhiyun# bit11: 0, required 115*4882a593Smuzhiyun# bit12: 0, DDR output buffer enabled 116*4882a593Smuzhiyun# bit31-13: 0 required 117*4882a593Smuzhiyun 118*4882a593SmuzhiyunDATA 0xFFD01424 0x0000F07F # DDR Controller Control High 119*4882a593Smuzhiyun# bit2-0: 111, required 120*4882a593Smuzhiyun# bit3 : 1 , MBUS Burst Chop disabled 121*4882a593Smuzhiyun# bit6-4: 111, required 122*4882a593Smuzhiyun# bit7 : 0 123*4882a593Smuzhiyun# bit8 : 0 , no sample stage 124*4882a593Smuzhiyun# bit9 : 0 , no half clock cycle addition to dataout 125*4882a593Smuzhiyun# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 126*4882a593Smuzhiyun# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 127*4882a593Smuzhiyun# bit15-12: 1111 required 128*4882a593Smuzhiyun# bit31-16: 0 required 129*4882a593SmuzhiyunDATA 0xFFD01428 0x00074510 130*4882a593SmuzhiyunDATA 0xFFD0147c 0x00007451 131*4882a593Smuzhiyun 132*4882a593SmuzhiyunDATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 133*4882a593SmuzhiyunDATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 134*4882a593Smuzhiyun# bit0: 1, Window enabled 135*4882a593Smuzhiyun# bit1: 0, Write Protect disabled 136*4882a593Smuzhiyun# bit3-2: 00, CS0 hit selected 137*4882a593Smuzhiyun# bit23-4: ones, required 138*4882a593Smuzhiyun# bit31-24: 0x07, Size (i.e. 128MB) 139*4882a593Smuzhiyun 140*4882a593SmuzhiyunDATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 141*4882a593SmuzhiyunDATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 142*4882a593SmuzhiyunDATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 143*4882a593Smuzhiyun 144*4882a593SmuzhiyunDATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) 145*4882a593Smuzhiyun# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 146*4882a593Smuzhiyun# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0 147*4882a593Smuzhiyun 148*4882a593SmuzhiyunDATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 149*4882a593Smuzhiyun# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 150*4882a593Smuzhiyun# bit3-2: 00, ODT1 controlled by register 151*4882a593Smuzhiyun# bit31-4: zero, required 152*4882a593Smuzhiyun 153*4882a593SmuzhiyunDATA 0xFFD0149C 0x0000FC11 # CPU ODT Control 154*4882a593Smuzhiyun# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 155*4882a593Smuzhiyun# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 156*4882a593Smuzhiyun# bit9-8: 1, ODTEn, never active 157*4882a593Smuzhiyun# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm 158*4882a593Smuzhiyun 159*4882a593SmuzhiyunDATA 0xFFD01480 0x00000001 # DDR Initialization Control 160*4882a593Smuzhiyun# bit0=1, enable DDR init upon this register write 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun# End of Header extension 163*4882a593SmuzhiyunDATA 0x0 0x0 164