Lines Matching refs:DDR
50 # bit24: 1= enable exit self refresh mode on DDR access
55 DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
67 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
78 DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
85 DATA 0xFFD01410 0x00000001 # DDR Address Control
100 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
104 DATA 0xFFD01418 0x00000000 # DDR Operation
105 # bit3-0: 0x0, DDR cmd
108 DATA 0xFFD0141C 0x00000652 # DDR Mode
109 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
110 # bit0: 0, DDR DLL enabled
111 # bit1: 1, DDR drive strenght reduced
112 # bit2: 1, DDR ODT control lsd disabled
114 # bit6: 0, DDR ODT control msb disabled
118 # bit12: 0, DDR output buffer enabled
121 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
159 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
163 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
177 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
178 # bit0=1, enable DDR init upon this register write