1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# (C) Copyright 2011 3*4882a593Smuzhiyun# Jason Cooper <u-boot@lakedaemon.net> 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun# Based on work by: 6*4882a593Smuzhiyun# Marvell Semiconductor <www.marvell.com> 7*4882a593Smuzhiyun# Written-by: Siddarth Gore <gores@marvell.com> 8*4882a593Smuzhiyun# 9*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun# 11*4882a593Smuzhiyun# Refer doc/README.kwbimage for more details about how-to configure 12*4882a593Smuzhiyun# and create kirkwood boot image 13*4882a593Smuzhiyun# 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun# Boot Media configurations 16*4882a593SmuzhiyunBOOT_FROM spi 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun# SOC registers configuration using bootrom header extension 19*4882a593Smuzhiyun# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun# Configure RGMII-0/1 interface pad voltage to 1.8V 22*4882a593SmuzhiyunDATA 0xFFD100e0 0x1b1b1b9b 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunDATA 0xFFD20134 0xbbbbbbbb 25*4882a593SmuzhiyunDATA 0xFFD20138 0x00bbbbbb 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun#Dram initalization for SINGLE x16 CL=5 @ 400MHz 28*4882a593SmuzhiyunDATA 0xFFD01400 0x43000c30 # DDR Configuration register 29*4882a593Smuzhiyun# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 30*4882a593Smuzhiyun# bit23-14: zero 31*4882a593Smuzhiyun# bit24: 1= enable exit self refresh mode on DDR access 32*4882a593Smuzhiyun# bit25: 1 required 33*4882a593Smuzhiyun# bit29-26: zero 34*4882a593Smuzhiyun# bit31-30: 01 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunDATA 0xFFD01404 0x39543000 # DDR Controller Control Low 37*4882a593Smuzhiyun# bit 4: 0=addr/cmd in smame cycle 38*4882a593Smuzhiyun# bit 5: 0=clk is driven during self refresh, we don't care for APX 39*4882a593Smuzhiyun# bit 6: 0=use recommended falling edge of clk for addr/cmd 40*4882a593Smuzhiyun# bit14: 0=input buffer always powered up 41*4882a593Smuzhiyun# bit18: 1=cpu lock transaction enabled 42*4882a593Smuzhiyun# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 43*4882a593Smuzhiyun# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 44*4882a593Smuzhiyun# bit30-28: 3 required 45*4882a593Smuzhiyun# bit31: 0=no additional STARTBURST delay 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunDATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 48*4882a593Smuzhiyun# bit3-0: TRAS lsbs 49*4882a593Smuzhiyun# bit7-4: TRCD 50*4882a593Smuzhiyun# bit11- 8: TRP 51*4882a593Smuzhiyun# bit15-12: TWR 52*4882a593Smuzhiyun# bit19-16: TWTR 53*4882a593Smuzhiyun# bit20: TRAS msb 54*4882a593Smuzhiyun# bit23-21: 0x0 55*4882a593Smuzhiyun# bit27-24: TRRD 56*4882a593Smuzhiyun# bit31-28: TRTP 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunDATA 0xFFD0140C 0x00000833 # DDR Timing (High) 59*4882a593Smuzhiyun# bit6-0: TRFC 60*4882a593Smuzhiyun# bit8-7: TR2R 61*4882a593Smuzhiyun# bit10-9: TR2W 62*4882a593Smuzhiyun# bit12-11: TW2W 63*4882a593Smuzhiyun# bit31-13: zero required 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunDATA 0xFFD01410 0x0000000d # DDR Address Control 66*4882a593Smuzhiyun# bit1-0: 01, Cs0width=x8 67*4882a593Smuzhiyun# bit3-2: 10, Cs0size=1Gb 68*4882a593Smuzhiyun# bit5-4: 01, Cs1width=x8 69*4882a593Smuzhiyun# bit7-6: 10, Cs1size=1Gb 70*4882a593Smuzhiyun# bit9-8: 00, Cs2width=nonexistent 71*4882a593Smuzhiyun# bit11-10: 00, Cs2size =nonexistent 72*4882a593Smuzhiyun# bit13-12: 00, Cs3width=nonexistent 73*4882a593Smuzhiyun# bit15-14: 00, Cs3size =nonexistent 74*4882a593Smuzhiyun# bit16: 0, Cs0AddrSel 75*4882a593Smuzhiyun# bit17: 0, Cs1AddrSel 76*4882a593Smuzhiyun# bit18: 0, Cs2AddrSel 77*4882a593Smuzhiyun# bit19: 0, Cs3AddrSel 78*4882a593Smuzhiyun# bit31-20: 0 required 79*4882a593Smuzhiyun 80*4882a593SmuzhiyunDATA 0xFFD01414 0x00000000 # DDR Open Pages Control 81*4882a593Smuzhiyun# bit0: 0, OpenPage enabled 82*4882a593Smuzhiyun# bit31-1: 0 required 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunDATA 0xFFD01418 0x00000000 # DDR Operation 85*4882a593Smuzhiyun# bit3-0: 0x0, DDR cmd 86*4882a593Smuzhiyun# bit31-4: 0 required 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunDATA 0xFFD0141C 0x00000C52 # DDR Mode 89*4882a593Smuzhiyun# bit2-0: 2, BurstLen=2 required 90*4882a593Smuzhiyun# bit3: 0, BurstType=0 required 91*4882a593Smuzhiyun# bit6-4: 4, CL=5 92*4882a593Smuzhiyun# bit7: 0, TestMode=0 normal 93*4882a593Smuzhiyun# bit8: 0, DLL reset=0 normal 94*4882a593Smuzhiyun# bit11-9: 6, auto-precharge write recovery ???????????? 95*4882a593Smuzhiyun# bit12: 0, PD must be zero 96*4882a593Smuzhiyun# bit31-13: 0 required 97*4882a593Smuzhiyun 98*4882a593SmuzhiyunDATA 0xFFD01420 0x00000042 # DDR Extended Mode 99*4882a593Smuzhiyun# bit0: 0, DDR DLL enabled 100*4882a593Smuzhiyun# bit1: 0, DDR drive strenght normal 101*4882a593Smuzhiyun# bit2: 0, DDR ODT control lsd (disabled) 102*4882a593Smuzhiyun# bit5-3: 000, required 103*4882a593Smuzhiyun# bit6: 1, DDR ODT control msb, (disabled) 104*4882a593Smuzhiyun# bit9-7: 000, required 105*4882a593Smuzhiyun# bit10: 0, differential DQS enabled 106*4882a593Smuzhiyun# bit11: 0, required 107*4882a593Smuzhiyun# bit12: 0, DDR output buffer enabled 108*4882a593Smuzhiyun# bit31-13: 0 required 109*4882a593Smuzhiyun 110*4882a593SmuzhiyunDATA 0xFFD01424 0x0000F1FF # DDR Controller Control High 111*4882a593Smuzhiyun# bit2-0: 111, required 112*4882a593Smuzhiyun# bit3 : 1 , MBUS Burst Chop disabled 113*4882a593Smuzhiyun# bit6-4: 111, required 114*4882a593Smuzhiyun# bit7 : 0 115*4882a593Smuzhiyun# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 116*4882a593Smuzhiyun# bit9 : 0 , no half clock cycle addition to dataout 117*4882a593Smuzhiyun# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 118*4882a593Smuzhiyun# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 119*4882a593Smuzhiyun# bit15-12: 1111 required 120*4882a593Smuzhiyun# bit31-16: 0 required 121*4882a593Smuzhiyun 122*4882a593SmuzhiyunDATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 123*4882a593SmuzhiyunDATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 124*4882a593Smuzhiyun 125*4882a593SmuzhiyunDATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 126*4882a593SmuzhiyunDATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 127*4882a593Smuzhiyun# bit0: 1, Window enabled 128*4882a593Smuzhiyun# bit1: 0, Write Protect disabled 129*4882a593Smuzhiyun# bit3-2: 00, CS0 hit selected 130*4882a593Smuzhiyun# bit23-4: ones, required 131*4882a593Smuzhiyun# bit31-24: 0x07, Size (i.e. 128MB) 132*4882a593Smuzhiyun 133*4882a593SmuzhiyunDATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 134*4882a593SmuzhiyunDATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 135*4882a593Smuzhiyun 136*4882a593SmuzhiyunDATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb 137*4882a593SmuzhiyunDATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 138*4882a593SmuzhiyunDATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb 139*4882a593SmuzhiyunDATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 140*4882a593Smuzhiyun 141*4882a593SmuzhiyunDATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low) 142*4882a593SmuzhiyunDATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 143*4882a593Smuzhiyun# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 144*4882a593Smuzhiyun# bit3-2: 01, ODT1 active NEVER! 145*4882a593Smuzhiyun# bit31-4: zero, required 146*4882a593Smuzhiyun 147*4882a593SmuzhiyunDATA 0xFFD0149C 0x0000F80F # CPU ODT Control 148*4882a593SmuzhiyunDATA 0xFFD01480 0x00000001 # DDR Initialization Control 149*4882a593Smuzhiyun#bit0=1, enable DDR init upon this register write 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun# End of Header extension 152*4882a593SmuzhiyunDATA 0x0 0x0 153